Design & Reuse
5629 IP
401
2.5
Xilinx Ultra Scale NVME Host IP
The LDS NVME HOST K7U IP is one of the most flexible NVME HOST IP in the market. It has been done for beginners and expert in NVMe to drive NVMe PC...
402
2.5
Xilinx Ultra Scale Plus SATA HOST IP
The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_...
403
2.5
Xilinx ZYNQ NVME HOST IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
404
2.5
Virtex 7 GTX SATA 3 Host Controller
The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed grade 2 FPGA. The LDS SA...
405
2.5
NVMe Host Recorder on Mini-ITX Zynq 7
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The register file interface simplify the manag...
406
2.5
NVME-HOST-IP VIRTEX 7
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
407
2.5
ZYNQ SATA 3 AHCI Host Controller with Linux Driver
The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed gr...
408
2.0
80390 - DP80390 - Pipelined High Performance Microcontroller
The DP80390 is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller intended to operate with fast (typicall...
409
2.0
8051 - DP8051 - Pipelined High Performance Microcontroller
The DP8051 is an ultra high performance, speed optimized soft core, of a single-chip 8-bit embedded controller, intended to operate with fast (typical...
410
2.0
SATA 3 Host Controller on Xilinx Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS_SATA3_HO...
411
2.0
LDS SATA RECORDER ON KINTEX 7
...
412
2.0
ARINC 429 Synchronous Transmitter Receiver
The M429T1R1 macro implements a synchronous single-chip ARINC 429 Transmit and Receive Controller Macro capable of linking one CPU to one ARINC 429 bu...
413
2.0
QSPI - DQSPI - Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support -
The DQSPI is a revolutionary quad SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interface...
414
1.0
8051 - DQ8051 - Revolutionary Quad-Pipelined Ultra High Performance Microcontroller
The DQ8051 is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, designed to operate with fast (typicall...
415
1.0
I2C Master
The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is ca...
416
1.0
I2C MAster Slave
The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus...
417
1.0
I2C Slave
The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried ...
418
1.0
2692 - D2692 - Dual UART
The D26C92 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681 with added features and deeper FIFOs. It contains: 8 charac...
419
1.0
SATA 2 HOST ON CYCLONE 5 GX
The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA Cyclone V GX FPGA. The...
420
1.0
SATA Device Controller on Altera Arria II GX
The LDS SATA DEVICE AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The...
421
1.0
SATA Device on Stratix IV GX
The LDS SATA DEVICE STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA STRATIX IV GX FPGA. ...
422
1.0
SATA Device on Virtex 6
The LDS SATA DEVICE XV6 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA D...
423
1.0
SATA Host Controller
The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. Th...
424
1.0
SATA HOST Controller on Cyclone IV GX
The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The ...
425
1.0
SATA Host Controller on Spartan 6 LXT FPGA
The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is co...
426
1.0
SATA Host controller on Virtex 5 FXT
The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
427
1.0
SATA Host Controller on Virtex 6 LXT
The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA HOST XV6 IP is com...
428
1.0
SATA Host on Altera Arria II GX
The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The L...
429
1.0
SATA HOST Synchronous IP
The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
430
1.0
SATA III HOST Controller on Virtex 6
The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The LDS SATA 3 ...
431
1.0
SATA RECORDER ON VIRTEX 6
The LDS SATA RECORDER XV6 IP is a complete recorder system IP. It can be configured according the recording performance required and the quantity of ...
432
1.0
SATA RECORDER ON VIRTEX 7 GTX
...
433
1.0
Serial ATA Dual Host Controller
The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XV5...
434
1.0
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master. The MSPIS IP can be ...
435
1.0
VeriSilicon GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM
VeriSilicon GSMC 0.18um Synchronous Low Power Diffusion ROM compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic/A...
436
1.0
Universal Asynchronous Receiver / Transmitter
The macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a ser...
437
1.0
Universal Asynchronous Receiver Transmitter
The macro M16450, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a ser...
438
1.0
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can...
439
1.0
PSMBUS - DPSMBUS - SMBUS & PMBUS Master/Slave controller
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities. It can operate as a DPSMBUSM – Ma...
440
1.0
GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM
Based on GSMC 0.13um 1.5V/12V eFlash process, current design of the IP detects light with photodiode. When the incident light power is more than 70mW/...
441
1.0
Dual SATA Host controller on Virtex 5 FXT FPGA
The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XF5...
442
1.0
Synchronous Universal Asynchronous Receiver/Transmitter
The macro MUART, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a seri...
443
0.7692
makeChip - 22FDX Hosted Design Service Platform
makeChip is the innovative Hosted Design Service Platform (HDSP) developed by Racyics®. Targeted for start-ups, SMEs, research institutes and universi...
444
0.118
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user...
445
0.0
H.264 4K Decoder - Supports 4KP60, 4:2:2, 10Bits
The H.264 Decoder Core is a highly optimized, high resolution decompression engine targeted primarily at FPGAs. It is well suited for various applicat...
446
0.0
H.264 HD DECODER - Supports 1080p60. 4:2:2. 10 Bits
VYUsync’s H.264 1080p60, 4:2:2, 10-bit Decoder Core is a highly optimized, high resolution decompression engine targeted primarily at FPGAs. The leadi...
447
0.0
80390 - DP80390CPU - Pipelined High Performance Microcontroller
The DP80390CPU is an ultra high performance, speed optimized soft core, of a single-chip 8-bit embedded controller, intended to operate with fast (typ...
448
0.0
80390 - DP80390XP - Pipelined High Performance Configurable Microcontroller
The DP80390XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typic...
449
0.0
8051 - DP8051CPU - Pipelined High Performance Microcontroller
The DP8051CPU is an ultra high performance, speed optimized soft core, of a single-chip 8-bit embedded controller, intended to operate with fast (typi...
450
0.0
8051 - DP8051XP - Pipelined High Performance Configurable Microcontroller
The DP8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typica...