eTopus Technology IP Cores

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1851

0.118

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 65nm LL process

Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 65nm LL/RVT process....

1852

0.118

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm LL process

Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process....

1853

0.118

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm SP process

Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm SP/RVT Low-K Logic process....

1854

0.118

PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 50MHz - 300MHz, UMC 90nm LL process

Input 5MHz-300MHz, output 50MHz-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process....

1855

0.118

PLL (Frequency Synthesizer) IP, Input: 5MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process

Input 5M-500MHz, output 31.25M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process....

1856

0.118

PLL (Frequency Synthesizer) IP, Input: 66.66MHz, Output: 400MHz - 800MHz, UMC 0.13um HS/FSG process

Input 66.66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 0.13um HS/FSG Logic process....

1857

0.118

PLL (Frequency Synthesizer) IP, Input: 66MHz - 100MHz, Output: 400MHz - 800MHz, UMC 90nm SP process

Input 66M-100MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 90nm SP Logic process....

1858

0.118

PLL (Frequency Synthesizer) IP, Input: 80MHz - 150MHz, Output: 80MHz - 150MHz, UMC 0.13um HS/FSG process

Input 80M-150MHz, output 80M-150MHz, frequency synthesizable PLL, UMC 0.13um Logic EHS/FSG process....

1859

0.118

PLL (Mini-PLL) IP, Input: 20MHz - 200MHz, Output: 31.5MHz - 500MHz, UMC 65nm SP process

miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 31.5MHz and 500MHz, UMC 65nm SP/RVT Low-K Logic process....

1860

0.118

PLL (Spread Spectrum) IP, 20MHz - 70MHz, UMC 0.18um G2 process

UMC 0.18um GII Logic process 20MHz-70MHz delay-type spread-spectrum clock generator....

1861

0.118

PLL (Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/FSG process

5GHz SSCG with 25MHz reference clock, UMC 0.11um 20T HS/FSG Logic process....

1862

0.118

PLL (Spread Spectrum) IP, Input: 5MHz - 1280MHz, Output: 15.625MHz - 2000MHz, UMC 55nm LP process

Input 20M-135MHz, output 20M-135MHz SSCG, UMC 0.18um Logic process....

1863

0.118

PLL (Spread Spectrum) IP, UMC 40nm LP process

Input clock:8MHz, output clock range:720 ~ 1680MHz wide-range SSCG, UMC 40nm LP process....

1864

0.118

PLL (Spread Spectrum) IP, UMC 40nm LP process

Input clock range:5 ~ 1280MHz, output clock range:15.625 ~ 2000MHz wide-range SSCG, UMC UMC 40nm LP/LVT Low-K Logic process....

1865

0.118

DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 0.11um HS/FSG process

Input 100M~400MHz, Output 100M~400MHz DLL-based cell that generates two-channel DQS with 25% timing delay, UMC 0.11um HS/RVT Logic process....

1866

0.118

PLL IP, Input: 10MHz - 200MHz, Outout: 50MHz - 1000MHz, UMC 90nm SP process

This Phase-Locked Loop (PLL) based clock multiplier....

1867

0.118

PLL IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.13um SP/FSG process

Output frequency 25M~400MHz PLL, UMC 0.13um SP/FSG Logic process....

1868

0.118

DLL IP, Input: 18MHz - 45MHz, Output: 18 - 45MHz, UMC 90nm SP process

Input 18M-45MHz, output 18M-45MHz, timing generator DLL, UMC 90nm SP/RVT Low-K process....

1869

0.118

PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process

The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz, UMC 0.13um HS/FSG Logic process....

1870

0.118

PLL IP, Input: 20MHz - 24MHz, Output: 20MHz - 100MHz, UMC 0.5um process

Input 20M-24MHz, output 20M-100MHz, frequency synthesizable PLL, 0.5um Logic process....

1871

0.118

PLL IP, Input: 25MHz, Output: 156.25MHz, UMC 40nm LP process

Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for JitteRClean Mode. UMC 4...

1872

0.118

PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process

high speed clock generator using UMC 0.13um 1.2V HS process....

1873

0.118

PLL IP, Input: 32.768KHz, Output: 12MHz - 30MHz, UMC 90nm SP process

Input 32.768KHz, output 12M-30MHz, PLL, UMC 90nm SP/RVT Logic Low-K process....

1874

0.118

PLL IP, Input: 32.768KHz, Output: 12MHz - 48MHz, UMC 0.11um HS/FSG process

Input 32.768KHz, output 12M-48MHz, PLL, UMC 0.11um HS/Copper Logic process....

1875

0.118

PLL IP, Input: 32.768KHz, Output: 12MHz, UMC 0.153um G2 process

Input 32.768KHz, output 12MHz, PLL, UMC 0.153um GII Logic/MM process....

1876

0.118

PLL IP, Input: 372M - 540MHz, Output: 5MHz - 400MHz, UMC 0.13um HS/FSG process

Input 372M ~ 540MHz, output 5M ~ 400MHz, PLL, UMC 0.13um HS/FSG Logic process....

1877

0.118

PLL IP, Input: 372M - 540MHz, Output: 5MHz - 420MHz, UMC 0.11um HS/FSG process

Input 372M ~ 540MHz, output 5M ~ 420MHz, PLL, UMC 0.11um HS/FSG Logic process....

1878

0.118

DLL IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process

Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 25% delay in period of FREF, UMC 28nm Logic and Mi...

1879

0.118

ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process.

ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process....

1880

0.118

ULL Single Port SRAM with peri HVT, UMC 40nm LP process.

ULL Single Port SRAM with peri HVT, UMC 40nm LP process....

1881

0.118

DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

1882

0.118

DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process

DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process...

1883

0.118

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process...

1884

0.118

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process...

1885

0.118

DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process

DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process...

1886

0.118

DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz). UMC 0.13um HS FSG Logic Process

DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz). UMC 0.13um HS FSG Logic Process...

1887

0.118

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler....

1888

0.118

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler....

1889

0.118

Global Foundries 55nm LowPower LowK Process synchronous high density low power dual port SRAM memory compiler.

Global Foundries 55nm LowPower LowK Process synchronous high density low power dual port SRAM memory compiler....

1890

0.118

Global Foundries 55nm LowPower LowK Process synchronous high density low power dual port SRAM memory compiler.

Global Foundries 55nm LowPower LowK Process synchronous high density low power dual port SRAM memory compiler....

1891

0.118

Global Foundries 55nm LowPower LowK Process synchronous high density low power single port SRAM memory compiler.

Global Foundries 55nm LowPower LowK Process synchronous high density low power single port SRAM memory compiler....

1892

0.118

Ultra High Speed 1-Port Register File, 6TSRAM, Peri LVT/RVT

UMC 28nm Logic and Mixed-Mode High Performance Process Synchronous HVT+RVT Periphery Ultra-High-Speed One-Port Register File Compiler...

1893

0.118

Embedded flash controller

The embedded flash controller (EFC) is flash memory device controlling apparatus and developed based on the Embedded Flash Macro (EFM) of pFusion co. ...

1894

0.118

Embedded flash controller for UMC 55LP Spit Gate embedded Flash.

Embedded flash controller for UMC 55LP Spit Gate embedded Flash....

1895

0.118

Embedded synchronous single port SRAM/ROM memory controller with AXI slave port.

Embedded synchronous single port SRAM/ROM memory controller with AXI slave port....

1896

0.118

UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library

UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library...