Catalog of SIP Cores
System on Chip design resources
System on Chip design resources
July 6, 2026 -
An open chiplet standard backed by BMW and Bosch signals European ambition to reduce automotive chip dependency on single suppliers
automotiveworld.com
Allegro DVT has contributed video encoding and decoding semiconductor intellectual property (IP) to the CHASSIS programme’s Automotive Base Die chiplet, a 5nm integration hub designed to enable a standardised, open chiplet ecosystem for software-defined vehicles (SDVs). The Automotive Base Die is co-funded by BMW, imec, and Bosch through the European Chips Joint Undertaking (Chips JU).
Allegro DVT’s IP supports multi-resolution video pipelines for advanced driver assistance system (ADAS) cameras, surround view, and infotainment applications within the chiplet-based architecture. The solution is designed to address memory bandwidth, processing latency, and power consumption requirements across heterogeneous chiplet configurations connected via the Universal Chiplet Interconnect Express (UCIe) standard.