CAST Expands Functional Safety IP Line with ASIL B Ready SENT/SAE J2716 Receiver Core

Production-proven CSENT-RX core adds certified Safety-Enhanced version for automotive sensor-interface designs

Woodcliff Lake, NJ — July 9, 2026 — Semiconductor intellectual property provider CAST today announced the availability of a Safety-Enhanced version of its SENT/SAE J2716 Receiver IP core that is certified as ISO 26262 ASIL B Ready.

The new certification expands CAST’s growing portfolio of Functional Safety IP cores and gives automotive ASIC and FPGA developers a compact, low-risk receiver for Single Edge Nibble Transmission (SENT) sensor interfaces. The SENT Receiver core has been in production use by multiple customers since 2022, and a leading automotive semiconductor customer has already selected the new Safety-Enhanced version for two ASIL B projects.

SENT is widely used for reliable, high-resolution digital communication from automotive sensors to electronic control units. The CAST CSENT-RX core implements a configurable receiver compliant with the SAE J2716 standard, supporting both synchronous and asynchronous sensors and enabling data reception from one or multiple sensors over a single SENT line.

“Automotive developers increasingly need even small sensor-interface blocks to fit cleanly into the system safety case,” said Peter Dumin, product manager for CAST. “Already a proven SENT receiver, the ASIL B Ready Safety-Enhanced version of the core gives customers the added safety mechanisms, documentation, and independent certification evidence needed to reduce risk and accelerate ISO 26262-oriented development.”

The CSENT-RX core is now available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements additional protection mechanisms including CRC, extended parity, dual modular redundancy where needed, and fault-injection test support. It includes a Safety Manual; Failure Modes, Effects and Diagnostics Analysis (FMEDA); and an ASIL B Ready certificate issued by SGS-TÜV Saar GmbH. These deliverables help customers integrate the core into SoC-level safety analyses more efficiently and provide stronger evidence for meeting system-level functional safety goals.

Rich SENT Feature Set with Low Host Overhead

CSENT-RX supports SENT fast and slow channels; 4-, 6-, and 8-bit CRC checking; programmable glitch filtering; all SENT frame types; programmable fast-channel data length; Short and Enhanced Message Formats for the slow channel; and inverted SENT protocol operation.

To reduce host-processor load, the core provides fast-channel data mapping and an optional configurable receive FIFO. An external metadata port allows the system to add custom timestamps or other metadata into the received data packets. For synchronous sensors, CSENT-RX can generate programmable trigger pulses activated through software control or a dedicated hardware input, allowing up to four sensors to share a single physical SENT connection.

On the system side, CSENT-RX provides a 32-bit AMBA® APB or AXI4-Lite interface (optionally bridged to AXI5-Lite). It includes synthesis-time-defined reset values for control registers, a comprehensive interrupt set, and handshaking signals for integration with an external DMA controller. The design is LINT-clean, scan-ready, and uses a single clock domain for straightforward ASIC or FPGA implementation.

Technology-agnostic, the CSENT-RX can be mapped to ASIC technologies or any suitable FPGA device. Standard configurations can be implemented in as few as 6,000 ASIC gates, while Safety-Enhanced ASIL B Ready configurations range from 22,000 – to 31,000 gates. (See representative ASIC and FPGA results on the product page.)