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System on Chip design resources
System on Chip design resources
July 27, 2026 -
SAN JOSE, California – Muse Semiconductor, a subsidiary of GS Microelectronics US, Inc. (GSME) and a leading provider of multi-project wafer (MPW) services, and True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) announced today the formation of a University IP Access Program offering TCI Phase-Locked Loop (PLL) hard macros in select TSMC processes to students and researchers using Muse MPW services. The goal of the program is for students and faculty to achieve better research, by using silicon-proven commercial IP, so they can focus their attention on innovating the next generation of semiconductor technologies.
Both Muse and TCI have long histories of working closely with universities to promote and enable advanced research. We recognize that students and faculty face the challenge of sourcing commercial IP and managing tight budgets. This program seeks to make the process both easier and more cost effective. By leveraging the existing MPW service and support infrastructure of Muse with highly discounted commercial IP from True Circuits, the next generation of engineers can both improve the quality of their designs and learn how to work in a commercial environment.
“This is a tremendous opportunity for universities to have easy access to world-class PLL IP”, said Bill Isaacson, General Manager of Muse Semiconductor. “We are excited about this timely enhancement to our MPW tapeout service and to see universities benefit from working with real-world, proven IP.
“We are excited to support the growing number of students, even undergraduates, who are taking semiconductor courses and building chips”, remarked Brian Gardner, V.P. of Business Development at True Circuits. “Providing PLLs through the Muse University IP Access Program goes hand-in-hand with our other initiative of open sourcing our own AMS development software, JDE™.”
The University IP Access Program is designed to closely mirror commercial semiconductor IP deployment while maintaining appropriate intellectual property protection and foundry compliance. Universities will engage with Muse and sign appropriate NDAs and MPW service agreements directly with Muse. When a TCI PLL is requested, an amendment designating the PLL part number and research project will be provided by Muse and signed by the authorizing party. The PLL design kit will then be delivered to the designated university contact for the specific research project. Future PLL uses are encouraged, so simple amendments would be signed to add new PLLs for new projects.
Students and faculty doing advanced research are always in the process of invention and need a PLL with the flexibility to clock their designs, as their thinking evolves. They need a PLL with a breadth of features and programmability, so it is adaptable. TCI’s General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a 1-16 divider at the output. The outputs are 50% duty cycle for all output divider values. It delivers optimal jitter performance over all multiplication settings and is suitable for system clock, interface and general purpose applications where small size and low power are also important. Consistent with the TSMC processes offered for the Muse MPW program, TCI will offer the General Purpose PLL in TSMC 180nm, 65nm, 28nm and 16nm process nodes.
Students and faculty will be able to access PLL user guidelines, application notes and training videos via a self-service portal on the Muse website. Over time, additional resources will be available such as general PLL education material and an AI-assisted knowledge base for PLL and IP related questions. Additional support and assistance will be available to users, with first-level from Muse and second-level directly from TCI.
Arrangements are being made to finalize the University IP Access Program and update the Muse website so students and faculty will have easy access to this new PLL offering. We will keep you posted when this program goes live, and we encourage interested parties to reach out to us with questions or comments. Please feel free to contact:
Bill Isaacson, General Manager of Muse Semiconductor at bill@musesemi.com
Brian Gardner, V.P. of Business Development at True Circuits at bgardner@truecircuits.com
Muse Semiconductor is a leading provider of multi-project wafer (MPW) services, dedicated to supporting university researchers, startups, and commercial companies in bringing their chip designs to life across North America, Europe and Asia. With deep expertise in the TSMC ecosystem, Muse Semiconductor has played a critical role in enabling innovation and accelerating the prototyping phase for countless semiconductor projects.
GS Microelectronics US, Inc. (GSME) is a leading full-service semiconductor company offering comprehensive ASIC design, manufacturing, packaging, and test solutions. Leveraging advanced process technologies, GSME collaborates with customers across high-growth sectors such as high-performance computing, artificial intelligence, automotive, and IoT. From concept to silicon, GSME delivers the expertise and infrastructure needed to accelerate innovation and bring complex semiconductor products to market with speed and precision.
True Circuits, Inc. develops and markets a broad range of industry leading PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and electronics industries. TCI's robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world's leading foundries, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. Over the last 28 years, True Circuits has distinguished itself as the technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers' products with production volumes well into the billions.