Catalog of SIP Cores
System on Chip design resources
System on Chip design resources
August 24, 2026 -
The controller, PHY, security, and verification IP support 128 GT/s links and target rack-scale memory pools exceeding 100 TB.
by Luke James, allaboutcircuits.com
Synopsys announced what it calls the industry's first complete CXL 4.0 IP solution, combining a controller, security modules, a silicon-proven PHY, and verification IP for the latest generation of the Compute Express Link interconnect. The release comes roughly nine months after the CXL Consortium published the 4.0 specification in November, and it targets the memory bandwidth and capacity limits that increasingly govern AI system performance.
CXL 4.0 doubles the link rate over CXL 3.x, from 64 GT/s to 128 GT/s, by adopting a PCIe 7.0-based physical layer while retaining the 256-byte FLIT format and full backward compatibility. The specification also adds support for up to four retimers per link and native x2 link widths, both aimed at extending fabric reach across a rack. Synopsys' package is designed to carry designs from that specification into working silicon across CXL 4.0, 3.x, 2.0, and 1.x on a single unified architecture.