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September 28, 2026 -
Cadence’s PCIe 6.0 PHY and controller IP passed first-pass PCI-SIG compliance testing at 64 GT/s on TSMC N3.
By Leo Bien Durana, techporn.ph
Cadence Design Systems announced that its PHY and controller IP for the PCIe 6.0 specification, implemented on TSMC’s N3 process, achieved first-pass compliance at PCI-SIG’s compliance workshop in late July. The event was the industry’s first official compliance testing round for the PCIe 6.0 spec, and Cadence’s x8 subsystem was tested at the standard’s full 64 GT/s data rate.
The full subsystem, covering both PHY and controller, passed all official PCIe 6.0 compliance tests and is now listed on PCI-SIG’s Integrators List.
Marc Loinaz, VP of R&D for high-performance PHY at Cadence’s Silicon Solutions Group, said PCIe is a key scale-up interconnect for AI and HPC data centers, and that the first-pass result confirms the subsystem’s interoperability and production readiness.