October 27, 2026 -

From Spiking Neural Network to RISC-V Hardware in Minutes

Barcelona – The INTERA Neuromorphic SDK transforms a trained spiking neural network (SNN) into a deployable and measurable embedded application. Models trained in SNNTorch (or any NIR-compatible framework) are exported to the community-standard NIR format. The SDK then quantizes the network, compiles it with an MLIR-based compiler, maps supported operations onto INTERA neuromorphic accelerators, generates firmware, and deploys the result to a RISC-V FPGA platform while reporting accuracy, latency, and memory usage.

It is a real compiler not a runtime interpreter so there is no inference engine to port and no hand-written firmware. The core of the stack is open source, ensuring models are not locked into a proprietary format.

End-to-end flow: SNNTorch / LAVA-DL → NIR → MLIR → RISC-V / FPGA targets

Hardware Acceleration Support

The SDK supports three execution targets on the same board:

• RISC-V CPU (baseline)  – whole network on the host CPU; use as reference for speed-up measurement.
• Eagle  – Near-Memory Computing accelerator: synaptic matrix-vector products in  accelerator memory, neurons on the CPU.
• Eagle Spiking  – full layer (synapses + bias + neuron dynamics + spikes) in hardware, neuron    state kept in accelerator memory across timesteps.

Open Source & Community Standards

INTERA believes that neuromorphic computing thrives through open standards.
The software development kit (SDK) is built upon these standards, and INTERA is releasing its core components:

• NIR-native – models from SNNTorch, LAVA-DL and other compatible frameworks enter without a proprietary exporter.
• Open-source SNN-MLIR – dialect, NIR front-end and CPU lowering released under Apache-2.0 (GitHub, PyPI, arXiv 2606.09213).
• Built on LLVM/MLIR – the same infrastructure used across the AI and HPC industry. Open core for portability; INTERA accelerator backends for performance.

Why It Matters

Without the SDK, teams must contend with framework-specific formats, manual quantization, hand-written firmware, complex FPGA flows, and ad-hoc benchmarking. With the SDK they gain an open NIR pathway, automatic bit-exact integer quantization, compiler-generated code, automatic memory layout, one-command deployment, and integrated accuracy and performance reports without vendor lock-in.

Typical use cases include neuromorphic edge prototyping (taking an SNNTorch model to real RISC-V hardware in a single reproducible flow), accelerator evaluation against a CPU baseline, systematic SNN benchmarking of accuracy, latency and memory, and the seamless transfer of research models from NIR to deployable firmware without rewriting them.

Train with SNNTorch. Compile with MLIR. Run on Neuromorphic Hardware.

The INTERA Neuromorphic SDK gives engineering teams an open, standards-based path from spiking neural network research to optimized, deployable applications on RISC-V embedded platforms.

Interested in exploring a sparse or neuromorphic workload?

Reach out: sales@intera-group.com or click here LINK