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System on Chip design resources
November 3, 2026 -
A practical path to energy-efficient AI acceleration using standard semiconductor technology
Barcelona -- The rapid growth of artificial intelligence continues to drive unprecedented demand for computational power and energy efficiency. In conventional computing systems, data must continuously move between memory and processors to perform calculations, creating the well-known von Neumann bottleneck. This constant data shuttling results in high energy consumption, increased latency, and limited scalability, posing a fundamental challenge for the next wave of AI workloads.
In-memory analog computing (IMAC) has emerged as a promising alternative by performing computations directly where data is stored. This approach dramatically reduces data transfer and enables the massive parallelism required by neural-network workloads. However, many existing IMC solutions rely on emerging resistive memory (ReRAM) devices such as memristors. These technologies still face significant hurdles, including device variability, conductance drift, limited endurance, and the difficulty of maintaining stable multi-level states at scale.
INTERA has developed novel architecture that overcomes these limitations through a fully CMOS-based active circuit element called the Programmable Current Pulse Cell (PCPC). Each PCPC generates a programmable current that represents a synaptic weight, while the activation time encodes the input signal. The natural interaction between current amplitude and activation duration performs the multiplication of weight and input. The resulting charge contributions are then accumulated across a crossbar array, executing vector–matrix multiplication in a massively parallel and highly energy-efficient manner.
This analog in-memory computing (IMAC) approach delivers the efficiency benefits of analog IMC while remaining entirely compatible with standard CMOS manufacturing processes. By leveraging mature semiconductor technology, INTERA significantly reduces technological and production risks compared with solutions that depend on emerging memory devices.
Standard CMOS implementation — Benefits from proven, high-volume semiconductor manufacturing, enabling reliable large-scale integration and faster time-to-market.
Energy efficiency and throughput — Computations occur in place, minimizing data movement and supporting the high parallelism demanded by modern neural networks.
Lower technological risk — Avoids the variability, drift, and endurance challenges associated with ReRAM and other emerging non-volatile memories.
Scalable foundation for AI accelerators — Provides a practical pathway to next-generation processors that combine high computational density with substantially reduced power consumption and latency.
INTERA’s IMAC technology is designed to serve as the foundation for a new class of AI accelerators. Potential application domains include data-center AI processing, edge computing devices, robotics, autonomous systems, and Internet-of-Things platforms anywhere energy efficiency, low latency, and scalable performance are critical.
From both a technology and investment perspective, INTERA’s approach combines a novel computing architecture with a pragmatic implementation strategy grounded in mature semiconductor manufacturing. By delivering the efficiency advantages of analog in-memory computing while maintaining low technological risk, the company offers a promising pathway toward commercially viable, next-generation artificial-intelligence processors.
As the AI semiconductor market continues its rapid expansion and the demand for energy-efficient computing intensifies, INTERA’s CMOS-based IMAC architecture has the potential to become a disruptive foundation for the processors that will power the next era of artificial intelligence.
To learn more about our CMOS-based analog in-memory computing technology and discuss partnership opportunities, please visit INTERA at the SEMICON event, booth C2119.
Or contact us in advance via the following link INTERA CONTACT