Imperas announce the latest RISC-V test suites are now available free with riscvOVPsimPlus

RISC-V Architectural Validation test suites updated for the ratified extensions including Vectors, Crypto (scalar), Bit Manipulation, and the new addition of Embedded (E) extension

Oxford, United Kingdom, July 6^th, 2022 -- Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest RISC-V test suites and updates to the free riscvOVPsimPlus reference model, simulator and test suites. Independently developed Verification IP (VIP) plays an important role in any verification plan since RISC-V developers’ interpretation of the specification are best tested against an independent reference. Architectural Validation test suites are important for RISC-V to ensure hardware implementations are in line with expectations of the software ecosystem supporting RISC-V.

In May 2022 RISC-V International's Architectural Test SIG (formerly the compliance working group) moved to using a Python program/framework v3.0 to run compliance testing and no longer provides signatures or scripts to run targets against their tests. As a service to RISC-V processor developers, Imperas has ported the RVI tests to the Imperas test framework and makes them available as part of the Imperas test downloads. This means you can use all of the Imperas tests and all of the RVI tests from one simple make/bash framework. The RISC-V International tests have the -RVI suffix with further information available at https://www.ovpworld.org/riscvOVPsimPlus.

riscvOVPsimPlus includes Architectural Validation test suites totaling over 8.6 million instructions, available as open-source and include:

• New Test suites for Embedded (E) soon to be ratified specifications
• New Test suites for RV32/64 Zmmul recently ratified specifications
• Test suites updated for RV32/64IMC ratified specifications
• Test suites updated for RV32F, RV64F, and RV64D ratified specifications
• Test suite updated for RV32/64K Crypto (scalar) 1.0.0 ratified specification
• Test suite updated for RV32/64B Bit Manipulation 1.0.0 ratified specification
• Test suite updated for RISC-V Vectors 1.0.0 ratified specification

Configured: spec:1.0.0, xlen:32, elen:32, vlen:256, slen:256, FP:IEEE754
Note ImperasDV users can access other configs of spec, xlen, elen, vlen, slen

RISC-V Specifications supported in riscvOVPsimPlus

• RISC-V - Instruction Set Manual, Volume I: User-Level ISA (user_version)
  • Version 2.2 : User Architecture Version 2.2
  • Version 2.3 : Equivalent to User Architecture Version 20191213
• -RISC-V - Instruction Set Manual, Volume II: Privileged Architecture (priv_version)
  • Version 1.10 : Privileged Architecture Version 1.10
  • Version 1.11 : Privileged Architecture Version 1.11, equivalent to 20190608
  • Version 1.12 : Privileged Architecture Version 1.12, equivalent to 20211203
• RISC-V I Base ISA
• RISC-V E Embedded ISA
• RISC-V M Multiply/Divide
• RISC-V A Atomic Instructions
• RISC-V F Single precision floating point
• RISC-V D Double precision floating point
• RISC-V C Compressed instructions
• RISC-V S Supervisor mode
• RISC-V U User mode
• RISC-V N User-level interrupts
• RISC-V V Vector Extension (vector_version)
  • Version 0.7.1-draft-20190605 : Vector Architecture Version 0.7.1-draft-20190605
  • Version 0.8 : Vector Architecture Version 0.8
  • Version 0.9 : Vector Architecture Version 0.9
  • Version 1.0 : Vector Architecture Version 1.0 (frozen for public review)
• RISC-V B Bit Manipulation Extension (bitmanip_version)
  • Version 0.90 : Bit Manipulation Architecture Version v0.90-20190610
  • Version 0.91 : Bit Manipulation Architecture Version v0.91-20190829
  • Version 0.92 : Bit Manipulation Architecture Version v0.92-20191108
  • Version 0.93 : Bit Manipulation Architecture Version v0.93-20210110
  • Version 0.94 : Bit Manipulation Architecture Version v0.94-20210120
  • Version 1.0.0 : Bit Manipulation Architecture Version 1.0.0
• RISC-V K Cryptographic Extension (crypto_version)
  • Version 0.7.2 : Cryptographic Architecture Version 0.7.2
  • Version 0.8.1 : Cryptographic Architecture Version 0.8.1
  • Version 0.9.0 : Cryptographic Architecture Version 0.9.0
  • Version 0.9.2 : Cryptographic Architecture Version 0.9.2
  • Version 1.0.0-rc5 : Cryptographic Architecture Version 1.0.0-rc5
• RISC-V P DSP/SIMD Extension (dsp_version)
  • Version 0.5.2 : DSP Architecture Version 0.5.2
  • Version 0.9.6 : DSP Architecture Version 0.9.6

In addition, the following specification extensions are available to ImperasDV commercial users

• RISC-V H Hypervisor Extension (hypervisor_version)
  • Version 0.6.1 : Hypervisor Architecture Version 0.6.1
• RISC-V Debug Module (debug_version)
  • Version 0.13.2
  • Version 0.14.0
  • Version 1.0.0-STABLE-20220609

“With all the desi

gn freedoms that RISC-V offers, verification has never been more important to ensure full ecosystem support for new processor implementations,” said Simon Davidmann, CEO at Imperas Software Ltd. “The best test for a processor is simulation-based testing to verify the interaction between the software program and the hardware operation. Architectural Validation test suites, while not a complete verification plan, offer the basic confirmation necessary to sustain the ecosystem of software support. We are pleased to offer the latest suites for the key ratified specifications of Vectors, Bit Manipulation and Crypto plus the new Embedded E suite, all for free including commercial use, with riscvOVPsimPlus.”

Availability

The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.

Validation tests for the Vector extension and the privilege PMP (Physical Memory Protection) unit are available to Imperas users and are configured to users’ specific hardware option settings.

The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd generation designs. These customers, partners and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high performance computing. A select sample of these include - Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), OpenHW Group, MIPS Technology, Seagate Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public.

ImperasDV is available now, more details are available at Imperas.com/ImperasDV.

Imperas at the Design Automation Conference 2022 (DAC 59)
Imperas will participate at DAC 2022, July 10-14 in San Francisco, California. Please stop by and see the latest trends and developments for RISC-V Verification. For more details on all the presentations, talks, or to request a demo please visit www.imperas.com/industry-events.

About Imperas

Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP, and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.