Nuclei Releases the NI1000 Series General-Purpose Compute Core with Support for the VME Matrix Extension

November 9, 2026 -

Shanghai, China  – Nuclei, a leading provider of high-performance semiconductor IP processing solutions, today introduced the NI1000 RISC-V CPU IP, its first high-performance general-purpose AI processor IP to support the Vector Matrix Extension (VME). Compute requirements for AI chips keep diversifying: alongside dedicated NPUs, the need for high-performance general-purpose parallel compute cores is becoming ever more pronounced. Building on the RVV vector extension and the VME matrix extension to accelerate the full range of workloads, the NI1000 gives AI chip makers a single, unified general-purpose compute core.

Nuclei NI-Series CPU IP: Empowering AI Chips

The NI series is Nuclei’s dedicated processor product line for artificial-intelligence applications. It can be configured as any member of the 900 or the 1000 series; the VLEN of its RVV 1.0 vector processing unit (VPU) can be set to 512, 1,024, 2,048 or 4,096 bits, and every core within a cluster can be given its own independently configured VPU. Through the IOCP (IO Coherent Port), the NI core couples tightly with NPU accelerators while maintaining cache coherency, which reduces data-movement overhead. The NICE/VNICE interfaces support user-defined scalar and vector instructions, and the NICE interface can also be used for tightly coupled interaction with an NPU.

Figure 1: NI processor for an AI subsystem — example configuration

Important note: The NI-series CPU IP is not intended to replace NPU, GPU or other accelerator IP. It is designed to work alongside them, serving the accelerators on an AI SoC more effectively and giving AI chip companies a more complete overall solution.

Nuclei’s High-Performance General-Purpose AI Processor IP: NI1000

The NI1000 is built on a high-performance RV64 scalar core. It is compatible with the standard RISC-V software ecosystem, and provides general-purpose control and execution capability. Its core architecture combines three cooperating parts: a powerful general-purpose scalar processor; an ultra-wide native RVV vector unit that handles general-purpose parallel computing; and the VME matrix extension, which handles matrix multiplication at ordinary scales. The three hardware layers work together to raise general-purpose AI compute performance.

Figure 2: NI1000 core micro-architecture — scalar, vector and VME pipelines

Ultra-Wide RVV Vector Capability

The NI1000 supports native RVV vector widths of 1,024, 2,048 or 4,096 bits, with the hardware configurable from 1,024 to 4,096 bits to keep pace with steadily growing general-purpose compute requirements. It also supports the Vector-NICE interface, which lets users define custom instructions to accelerate specific vector operations.

VME Matrix Extension, Tightly Coupled with RVV in the Same Core

The NI1000 supports the VME (Vector Matrix Extension). VME is tightly coupled with the CPU and RVV within the same core and provides native matrix-operation instructions that raise matrix compute performance. VME shares its register file and execution units with RVV, adding only a small amount of area for the Matrix Tiles.

1. VME: advantages and positioning

• A balanced cost/performance point, complementing the NPU: VME fuses RISC-V general-purpose vector capability with dedicated matrix-accumulate capability, so that general-purpose computing and AI matrix computing are both served efficiently. Compared with IME, it has dedicated matrix-accumulate hardware and therefore higher energy efficiency on matrix operations; compared with AME, it dispenses with a full independent matrix register file and hardware matrix accelerator, keeping hardware overhead under control while retaining matrix compute efficiency. This makes it particularly well suited as the general-purpose parallel compute core alongside an NPU.
• Strong compatibility with the RISC-V software ecosystem: VME is built entirely on the RISC-V Vector Extension as its foundation and therefore inherits a solid software-ecosystem base. VME is expected to become the earliest standardised RISC-V Matrix Extension.

2. VME re-uses RVV extensively

The source operands of VME instructions re-use the RVV register file, and the cost of the VME execution units is fully absorbed by re-using the RVV execution units.

3. VME adds native matrix-operation instructions

VME adds a number of native matrix-operation instructions whose results are stored in dedicated Matrix Tiles. In addition, VME introduces native support for the FP8 data type.

4. VME adds four independent sets of Matrix Tiles – how they are used

• Data loading: the RVV registers are re-used; load instructions bring data from memory into the RVV vector registers Vr1 and Vr2.
• Multiply-accumulate: the VMMA instruction re-uses the RVV compute units to perform an outer-product multiplication of vector registers A and B, accumulating the (Vr1 × Vr2) products into the dedicated (N × N) matrix-accumulate Matrix Tiles.
• Storing results: each outer-product result can be accumulated continuously into the Matrix Tiles. Several Tiles operate in ping-pong fashion for parallel throughput, increasing parallelism.

5. Example of the performance gain from VME on the NI1000

Figure 3: Area and matrix performance of the NI1020 (VLEN 1024) with and without VME

Executing a 32×32 FP32 matrix multiplication under the VME matrix extension raises matrix-multiplication performance 2.5× for an overall area increase of only 15% (mostly attributable to the Matrix Tiles).

The NICE Extensible-Instruction Interface Supports System-Level Co-operation

The NI1000 provides the NICE/VNICE user-extensible instruction interfaces. NICE (Nuclei Instruction Co-unit Extension) is a user-extensible instruction mechanism of Nuclei CPU IP that lets users define their own extended instruction set on top of the chip’s standard general-purpose CPU core:

• The NI core provides a NICE interface for scalar instruction extensions, supporting single-cycle, multi-cycle and pipelined instruction types. The NI core’s NICE extension unit can host not only compute-type custom instructions; through a dedicated bus it can also access the core’s memory resources (such as the D-Cache) to maintain memory coherency with the main core.
• The NI core provides a NICE interface for vector instruction extensions, likewise supporting single-cycle, multi-cycle and pipelined instruction types.

Users can add custom instructions for their own applications and so extend the NI core into a dedicated processor further strengthened for the AI domain.

Takeaway 1: RISC-V Is the Best Suited ISA to AI Chips

Seen from the instruction-set perspective, RISC-V is the only architecture able to fill all three roles inside an AI SoC at once: main control core, compute core and boot core. RISC-V can serve as a high-performance AI main core and can equally be trimmed down to a minimal embedded MCU without an MMU. Vector and matrix AI extension instructions re-use a single standard, vendor-defined instruction extensions are supported, and cloud, edge and endpoint devices share the same underlying operators, drivers and development frameworks — substantially lowering the cost of duplicated software development.

Takeaway 2: The NI1000 Meets the Core Requirements AI Chips Place on a Compute Core

Figure 4: The three RISC-V roles in an AI SoC — compute cores, main control cores and boot core

An AI chip compute core needs strong vector parallel compute

• The NI1000 natively supports an RVV 1.0 vector unit, with VLEN configurable at 512, 1,024, 2,048 or 4,096 bits.
• The NI1000 supports multiple precisions, including FP16, BF16 and INT8, carrying AI operators efficiently.
• The NI1000 can be extended to support the VME vector matrix extension.

An AI chip compute core needs tightly coupled custom hardware acceleration

• The NI1000 can be extended with custom scalar and vector instructions through the NICE/VNICE interfaces, and supports tightly coupled integration with NPU accelerators to fit heterogeneous AI compute architectures.

An AI chip compute core needs a mature RISC-V software ecosystem

• The RVV supported by the NI1000 enjoys a rapidly growing software ecosystem for AI.
• The VME supported by the NI1000 re-uses the RVV software ecosystem, saving development time on the accompanying AI software stack.

An AI chip compute core needs high-bandwidth memory access and efficient data exchange with on-chip accelerators

• The NI1000 supports a multi-level cache architecture: L1 local memory and I/D caches, plus a cluster-shared cache.
• The NI1000 supports the IOCP cache-coherent port, maintaining cache coherency with on-chip NPUs and accelerators and reducing data-movement overhead.
• The NI1000 supports the VLM (Vector Local Memory) port, providing a dedicated high-throughput data path.

In summary, the NI1000 high-performance general-purpose parallel compute core uses RVV and VME acceleration to empower the development of AI chips. Within the open RISC-V ecosystem, the NI1000 can take on the role of the general-purpose AI compute core in an AI chip, and can equally be tightly coupled with NPUs and other accelerators to form a more complete overall solution. Nuclei will continue to build on the open RISC-V ecosystem as its foundation, providing AI chip companies with full-stack support from main control core and compute core through to complete subsystem solutions.

For more information about Nuclei and its RISC-V solutions, please visit www.nucleisys.com.

About Nuclei

Established in 2018, Nuclei System Technology is a global leader in RISC-V processor IP and comprehensive SoC solutions. As a pioneer in the RISC-V ecosystem, Nuclei is dedicated to “Empowering the Computing Revolution of the Future” through a robust portfolio of high-performance, low-power, and highly configurable processor cores.

Nuclei offers a complete spectrum of RISC-V IPs, including the N/U (32-bit) and NX/UX (64-bit) series for general-purpose and application processing, as well as specialized lines for Automotive (NA), Security (NS), and Intelligence/AI (NI). Notably, Nuclei’s NA series stands as the world’s first RISC-V processor IP to achieve the ISO 26262 ASIL-D functional safety certification, cementing its position as a trusted partner for mission-critical industries.

Beyond standalone CPU cores, Nuclei is a champion of the “IP 2.0” Subsystem model. This approach provides clients with fully integrated SoC subsystems, including bus fabrics, accelerators, and complete open-sourced software stacks, reducing front-end development tasks by up to 80% and significantly accelerating time-to-market.

With over 350 customers and a proven track record in AI, Automotive, 5G, Industrial Control, and IoT, Nuclei continues to drive the global adoption of open-standard architectures from its headquarters in Shanghai and expanding regional hubs.