Unleash Next-Gen Speeds with Silicon-Proven USB 3.0 PHY IP Cores with Type-C Support in Multiple Process Nodes

March 4, 2024. – T2M^IP, announces high-performance communication solutions with its advanced USB 3.0 PHY IP cores featuring Type-C support, available in three cutting-edge process nodes: 7nm, 12nm, 22nm and 28nm. This comprehensive offering empowers designers to seamlessly integrate the latest USB technology into their next-generation SoCs, catering to diverse applications like AI chips, automotive electronics, and beyond.

The USB 3.0 PHY IP cores supports industry-leading data transfer rates of 5Gbps (USB 3.2 Gen1), 10Gbps (USB 3.2 Gen2), and 20Gbps (USB 3.2 Gen2x2), surpassing the limitations of traditional USB 3.0 implementations. Offered in 7nm, 12nm, 22nm and 28nm process nodes, catering to a wide range of power, performance, and cost requirements, the IP Cores also integrates seamlessly with the latest USB Type-C connector, providing a user-friendly experience and future-proofing designs for long-term applicability. This IP core with USB-C capabilities can accomplish functions of different applications, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control and testing.

The USB 3.0 PHY IP cores come with complementary USB 3.0 controllers, that support Host, Device and OTG functions ensuring seamless integration and reduced development time. Backed by extensive silicon and production-proven results, guaranteeing reliable operation in real-world applications the IP Core minimizes development risks by providing a pre-verified and production-ready solution. Perfect for integrating high-bandwidth connectivity into a wide range of emerging technologies demanding superior performance and user-friendliness. The USB 3.0 IP Cores is compliant with PIPE 3.0 and is backwards compatible for Legacy, High Speed and Full speed USB support. Operating at a Voltage range of 1.1V and 3.3V, the solution focuses on low power efficiency with support for low jitter automatically calibrated oscillator for crystal-less mode, a dynamic equalization circuit, and a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection.

The USB 3.0 PHY & Controllers IP cores enables high-speed data transfer for training and inference tasks in AI processors, while benefiting from the user-friendly Type-C connection. The same facilitates fast and reliable communication between various in-car components, supporting advanced features like ADAS and autonomous driving functionalities, with the added convenience of Type-C connectors.

USB 3.2 Gen1 and Gen2 PHY and Controller IP cores stand at the forefront of high-speed data transfer technology, offering versatility, reliability, and proven success in mass production SoCs. In addition to USB IP Core, T2M ‘s broad silicon Interface IP Core Portfolio includes HDMI, Display Port, MIPI (CSI, DSI UniPro, UFS, RFFE, I3C), ), PCIe, DDR, 1G Ethernet, V-by-One, programmable SerDes, OnFi and many more, available in major Fabs in process geometries as small as 7nm.

Availability:

These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M:

T2M^IP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com

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