Design & Reuse
1899 IP
901
1.0
USB1.1 PHY - SMIC130nm Eflash
...
902
1.0
USB1.1 PHY-SMIC15_USB11_01
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
903
1.0
USB1.1 PHY-SMIC25_USB11_01
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
904
1.0
USB1.1 PHY-SMIC25_USB11_02
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
905
1.0
USB1.1PHY controller
...
906
1.0
USB2.0 OTG PHY
...
907
1.0
USB2.0 OTG PHY
The INNO USB 2.0 PHY conforms to the specification of UTMI+ level 3 Revision 1.0 (USB 2.0 Transceiver Macrocell Interface Plus) and has excellent perf...
908
1.0
USB2.0 PHY - SMIC 110nm generic
...
909
1.0
USB2.0 PHY - SMIC 153nm Logic
...
910
1.0
USB2.0 PHY - SMIC 180nm Logic
...
911
1.0
USB2.0 PHY - SMIC130nm Eflash
...
912
1.0
USB2.0/eUSB2.0 PHY & Controller
USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications. Innosilicon provides a comprehensive se...
913
1.0
USB3.0 PHY - SMIC 55nm Eflash
High speed analog circuits for USB3.0 PHY application 745um*620um...
914
1.0
USB3.1/3.0 PHY & Controller
The Innosilicon USB3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface fo...
915
1.0
USB3.2 PHY & Controller
INNOSILICON™ USB3.2 Controller and PHY IP is a highly customizable IP module that converts high-speed serial data into parallel data, and is compliant...
916
1.0
PSMBUS - DPSMBUS - SMBUS & PMBUS Master/Slave controller
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities. It can operate as a DPSMBUSM – Ma...
917
1.0
CSMC 0.13um USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives dat...
918
1.0
GSMC 0.15um 1.2V/3.3V PCI I/O Cells
VeriSilicon GSMC 0.15um 1.2V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) ...
919
1.0
GSMC 0.18um PCI I/O Cells Library
VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC)...
920
1.0
GSMC 0.18um USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver. It receives data via DP and DM, and transfers data to USB1.1 core via RCV, VM and VP. It is design...
921
1.0
GSMC 0.25um 2.5V/3.3V PCI I/O Cell Library
VeriSilicon GSMC 0.25um 2.5V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) ...
922
1.0
TSMC 55nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...
923
1.0
GSMC0.18um PCI I/O Cells DUP Library
VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC)...
924
1.0
RTP / UDP / IP Hardware Stack for H.264/H.265 NAL Video Streams Packet Processing
The Digital Blocks DB-RTP-UDP-IP-NAL IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor...
925
1.0
RTP / UDP / IP Hardware Stack for Raw, Uncompressed RGB/YUV Video Streams
The Digital Blocks DB-RTP-UDP-IP-AV IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor ...
926
1.0
Multi-PHY Receiver Link Controller
CD12842M8LRM3BM4AIP312P5 is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macr...
927
1.0
Super-Speed Plus USB 3.2 Hub Controller
USB3.2 SuperSpeed Hub The Super Speed Plus USB bus is implemented as a separate dual-simplex dual lane data path consisting of two uni-directional di...
928
0.3729
I2C Controller & PHY
DTI I2C Controller provides the logic consistent with NXP I2C specification to support the communication of low-speed integrated circuits through I2C ...
929
0.3729
PCI/PCIX Interface 1.8V Oxide Device- TSMC 22nm 22ULP,ULL
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
930
0.3729
PCI/PCIX Interface 1.8V Oxide Device - TSMC 28nm 28HP, 28LP, 28ULP, 28HPL, 28HPC, 28HPC+, 28HPM
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
931
0.3729
PCI/PCIX Interface 2.5V Device - TSMC 28nm 28HP (CLN28HP)
Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, S...
932
0.3729
PCI/PCIX Interface 2.5V Device - TSMC 40nm 40G (CLN40G)
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...
933
0.3729
PCI/PCIX Interface 2.5V Device - TSMC 40nm 40LP (CLN40lp)
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully complian...
934
0.3729
Dolphin I2S Controller & PHY
DTI I2S Controller provides an interface between system bus and Inter-IC Sound devices. The controller is compliant with NXP Inter-IC Sound Bus Specif...
935
0.3729
Dolphin I3C Controller & PHY
DTI I3C Controller provides the logic consistent with NXP I3C specification to support the communication of low-speed integrated circuits through I3C ...
936
0.118
V-by-One Receiver
Analog part of 600Mbps to 4Gbps 4-lane V-By-One receiver with embedded CDR circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process....
937
0.118
V-by-one(VBO) high speed receiver(RX) (includes PMA, PCS, and controller).
V-by-one(VBO) high speed receiver(RX) (includes PMA, PCS, and controller)....
938
0.118
V-by-one(VBO) high speed transmitter(TX) (includes PMA, PCS, and controller).
V-by-one(VBO) high speed transmitter(TX) (includes PMA, PCS, and controller)....
939
0.118
16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provide optimization of pow...
940
0.118
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process
28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process...
941
0.118
28nm HPC USB3.1 gen2 PHY(10Gbps)
28nm HPC USB3.1 gen2 PHY(10Gbps)...
942
0.118
28nm HPC x4 lane 10 Gbps SERDES
28nm HPC x4 lane 10 Gbps SERDES...
943
0.118
28nm HPC+ USB3.1 gen2 PHY(10Gbps)
28nm HPC+ USB3.1 gen2 PHY(10Gbps)...
944
0.118
SATA Controller IP, SATA Gen-3 Host, Soft IP
SATA AHCI host controller with PVCI/AHB/AXI interface....
945
0.118
SATA Controller IP, SATA Gen-3, Soft IP
SATA Device Controller....
946
0.118
SATA II PHY IP, Gen-2, 1 - port, UMC 0.18um G2 process
1.5G/3.0Gbps 1 port Serial ATA PHY and ESATA, UMC 0.18um GII Logic process....
947
0.118
SATA II PHY IP, Gen-2, UMC 0.11um HS/AE process
3G/1.5G Serial ATA PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process....
948
0.118
SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
Serial ATA (SATA) physical layer that provides a complete range of host and device functions, UMC 0.13um HS/FSG Logic process....
949
0.118
SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
Over sampling 1 port 3G/1.5G SATA PHY, UMC 0.13um HS+LL/FSG Logic process....
950
0.118
SATA II PHY IP, Gen-2, UMC 90nm SP process
Serial ATA I II PHY, UMC 90nm SP/RVT Low-K Logic process....