Design & Reuse
Catalog of SIP Cores
System on Chip design resources
6237 IP
51
0.0
Synopsys Memory, Logic, IO for UMC 40ULP
Synopsys provides designers with a broad portfolio of high-speed, high-density and low-power memory compilers and logic libraries. The Synopsys Duet P...
52
16.0
8b/10 Decoder
The 8b10b line code is widely used to achieve DC-balance and bounded disparity when transmitting serial data over a medium. It ensures enough state tr...
53
16.0
AHB-Lite APB4 Bridge
The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protoco...
54
16.0
AHB-Lite General Purpose Memory Module
The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defi...
55
16.0
AHB-Lite Multilayer Switch
The Roa Logic AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It al...
56
16.0
AHB-Lite Timer
The Roa Logic AHB-Lite Timer IP is a fully parameterized soft IP implementing a user-defined number of timers and functions as specified by the RISC-V...
57
16.0
RISC-V Compliant Platform Level Interrupt Controller
Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of i...
58
16.0
RISC-V Compliant Platform Level Interrupt Controller
Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of i...
59
16.0
RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of ...
60
16.0
APB4 General Purpose Input/Output Module
The APB4 GPIO Core is fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design. The IO a...
61
16.0
APB4 Multiplexer
The AMBA APB v2.0 bus protocol – commonly referred to as APB4 – defines a low-cost interface that is optimized for minimal power consumption and redu...
62
10.0
64x8 Bits OTP (One-Time Programmable) IP, UM- 55nm ULP standard CMOS core logic Process
The AT64X8U55ULP6AA is organized as a 64-word by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 55nm ULP standard ...
63
5.0
AGILEX 7 R-Tile NVME HOST IP
Gen5 NVMe Host IP on AGILEX7 R-Tile It enables random access, sequential access, Read/Write access and multi-user access. To show these features, s...
64
5.0
Xilinx UltraScale Plus NVME Hhost IP
The LDS NVME HOST ZUP IP is one of the most flexible NVME HOST IP in the market. It has been done for beginners and expert in NVMe to drive NVMe PC...
65
5.0
Kintex Ultra Scale Plus NVMe Host IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The LDS NVME HOST IP provides two interfaces : * On...
66
5.0
NOE SAN IP
Enabling Remote-Attached Storage on FPGA-Based Embedded Systems over 10G/25G/50G/100G/200G/400GbE The NOE_SAN_IP adopts an open SAN protocol named AT...
67
5.0
Logic Design Solutions - Design Services
Logic Design Solutions has a deep knowledge of FPGA & IP design. We have an expertise in fast designs and for over 20 years? experience in FPGA/PLD De...
68
5.0
Polarfire NVMe Host Recorder
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The register file interface simplify the manag...
69
5.0
Polarfire SoC NVMe Host
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The register file interface simplify the manag...
70
5.0
ARINC 429 IP
The M429GEN IP implements a synchronous single-chip ARINC 429 Transmit and Receive Controller capable of linking one CPU to one or several ARINC 429 ...
71
5.0
Artix Ultra Scale Plus NVMe Host IP Gen4
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. - The LDS NVME HOST IP provides two interfaces : o One C...
72
5.0
Ethernet MAC 10G SFP
The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification. It is designed to be con...
73
5.0
NVME Host IP
The new NVME-HOST-IP of Logic Design Solutions enables now random access in addition to the existing sequential access and multi-user access. FAT32 fi...
74
5.0
EXFAT IP Soft Core for NVMe
The EXFAT IP Soft Core for NVMe supports any disk size and enables to reach the same speed as in raw format. One directory is created for each recordi...
75
2.5
FAT32 IP Soft Core for NVMe
FAT32 IP Soft Core for NVMe...
76
2.5
SATA 3 Host Controller on ARRIA V FPGA
The LDS SATA 3 HOST AR5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Stratix IV GX FPGA. T...
77
2.5
SATA 3 Host Controller on ZYNQ
The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS SATA 3 HOST...
78
2.5
SATA 3 HOST IP on ARRIA 10 FPGA
The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The L...
79
2.5
SATA Device Controller on Kintex 7
The LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The LDS SATA...
80
2.5
SATA HOST 3 ON KINTEX 7 Ultrascale
The LDS SATA 3 HOST XK7U IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 Ultrascale speed grade 2 FPGA. The...
81
2.5
SATA HOST 3 ON VIRTEX 7 GTH
...
82
2.5
SATA Host 6G Controller on Kintex 7
The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The LDS SATA 3 ...
83
2.5
SATA Host on Xilinx Zynq Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS SATA 3 H...
84
2.5
LDS SATA RECORDER IP ON ARTIX 7
...
85
2.5
LDS SATA RECORDER ON ZYNQ
...
86
2.5
Xilinx Kintex 7 NVME HOST IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
87
2.5
Xilinx Ultra Scale NVME Host IP
The LDS NVME HOST K7U IP is one of the most flexible NVME HOST IP in the market. It has been done for beginners and expert in NVMe to drive NVMe PC...
88
2.5
Xilinx Ultra Scale Plus SATA HOST IP
The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_...
89
2.5
Xilinx ZYNQ NVME HOST IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
90
2.5
Virtex 7 GTX SATA 3 Host Controller
The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed grade 2 FPGA. The LDS SA...
91
2.5
NVMe Host Recorder on Mini-ITX Zynq 7
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The register file interface simplify the manag...
92
2.5
NVME-HOST-IP VIRTEX 7
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
93
2.5
ZYNQ SATA 3 AHCI Host Controller with Linux Driver
The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed gr...
94
2.0
SATA 3 Host Controller on Xilinx Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS_SATA3_HO...
95
2.0
LDS SATA RECORDER ON KINTEX 7
...
96
2.0
ARINC 429 Synchronous Transmitter Receiver
The M429T1R1 macro implements a synchronous single-chip ARINC 429 Transmit and Receive Controller Macro capable of linking one CPU to one ARINC 429 bu...
97
2.0
RV12 - RISC-V Processor
The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of ...
98
1.0
I2C Master
The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is ca...
99
1.0
I2C MAster Slave
The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus...
100
1.0
I2C Slave
The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried ...