Catalog of SIP Cores
System on Chip design resources
System on Chip design resources
May 21, 2026 -
High-performance computing and data-intensive systems are increasingly constrained by data movement rather than compute. From scientific experiments to AI training clusters and datacenters, continuous data streams must be processed at extremely high speeds while meeting strict latency, power, and storage requirements.
This 30-minute presentation explores how hardware-based lossless compression in FPGA and ASIC designs reduces bandwidth and memory demands without compromising data integrity or accuracy. It examines deterministic, low-latency architectures integrated with Ethernet, PCIe, high-bandwidth memory, and storage systems. Key algorithms including LZ4, Snappy, GZIP/DEFLATE/Zlib, and Zstandard are compared to highlight trade-offs between compression ratio, throughput, and resource utilization.
Speaker: Dr.Calliope-Louisa Sotiropoulou