Catalog of SIP Cores
System on Chip design resources
System on Chip design resources
July 28, 2026 -
Palo Alto, California -- IP Cores, Inc. (http://www.ipcores.com) has announced the release of the LZR4D core, a single-engine ultralow-latency hardware decompressor for the widely used LZ4 lossless compression format. The LZR4D produces 256 bits of decompressed output per clock cycle from a single decompression engine, placing its throughput in the terabit-per-second class at the clock frequencies achievable in modern semiconductor processes.
"The LZR4D core represents a significant step forward in hardware decompression performance," said Dmitri Varsanofiev, CTO of IP Cores, Inc. "A single LZR4D engine sustains 256 bits of output per clock, a multiple of the throughput of decompressor cores currently available on the market, without resorting to arrays of parallel engines and the block-level stream splitting they require. Combined with a latency of under 30 clock cycles, the core adds only 10 to 20 nanoseconds of decompression delay in advanced semiconductor nodes, making on-the-fly decompression practical in the data path of storage controllers, memory subsystems, and network processors."
LZR4D
The LZR4D core implements lossless decompression of data compressed in the LZ4 format. Unlike conventional few-bytes-per-clock or token-per-clock designs, the LZR4D resolves multiple LZ4 sequences concurrently within a single decompression engine, sustaining an output rate of 256 bits (32 bytes) of decompressed data per clock cycle on a single compressed stream. At the multi-gigahertz clock rates of advanced process nodes, this corresponds to terabit-class decompression throughput in a single engine, with no need to split data into independently compressed blocks across an array of slower decompressors.
The core's decompression latency is below 30 clock cycles, which translates to an end-to-end decompression delay of 10 to 20 nanoseconds in advanced semiconductor nodes. This ultralow, deterministic latency allows the LZR4D to be placed directly in latency-critical data paths, such as compressed memory tiers, CXL-attached memory expanders, solid-state storage controllers, enterprise storage appliances, and in-network data processing, where the decompression step was previously a bottleneck.
For more information about IP Cores' product line, please visit www.ipcores.com/LZ4_ip_core_LZR4D.htm.
LZ4 Compression Format
LZ4 is a lossless data compression (https://en.wikipedia.org/wiki/Lossless_compression) algorithm and format focused on very high compression and decompression speed (https://en.wikipedia.org/wiki/LZ4_(compression_algorithm)). LZ4 belongs to the LZ77 family of byteoriented dictionary compression schemes (https://en.wikipedia.org/wiki/LZ77_and_LZ78) and is widely deployed in file systems, databases, operating system kernels, and storage and networking equipment, where its decompression speed makes transparent compression practical.
About IP Cores, Inc.
IP Cores (http://www.ipcores.com) is a long established California company in the field of security, error correction, data compression, and DSP IP cores. Founded in 2004, the company provides hardware IP cores for embedded, communications and storage fields, including lossless data compression and decompression cores for the LZ4, LZRW and GZIP/Deflate formats, AES-based ECB/CBC/OCB/CFB, AESGCM and AES-XTS cores, MACsec 802.1AE, IPsec and SSL/TLS protocol processors, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), post-quantum cryptography (PQC) accelerators for ML-KEM (FIPS-203), ML-DSA (FIPS- 204) and SLH-DSA (FIPS-205), public-key accelerators for RSA and elliptic curve cryptography (ECC), true random number generators (TRNG), cryptographically secure pseudo-random number generators (CS PRNG), secure SHA and MD5 cryptographic hashes, low-latency and low-power fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, LDPC, BCH and Viterbi forward error correction (FEC) decoder cores.