Silicon-Proven D2D Interconnect IP Cores for High-Speed, Scalable Chiplet Connectivity

August 10, 2026 -

Applications such as artificial intelligence (AI), high-performance computing (HPC), networking, automotive electronics, and data-centre processors increasingly require high-bandwidth, low-latency communication between multiple dies while maintaining power efficiency and simplifying system integration.

To address these requirements, T2M is introducing its partner’s silicon-proven D2D (Die-to-Die) Interconnect IP Core, available under a flexible WhiteBox licensing model with unlimited usage. Based on the Advanced Interface Bus (AIB) architecture, the IP core enables efficient 32-bit AXI data transfers between dies, combining high throughput, ultra-low latency, and straightforward integration for advanced multi-die SoCs.

Optimized Architecture for High-Speed Multi-Die Communication

The D2D Interconnect IP Core supports both Controller and Target configurations, enabling efficient AXI-based communication across separate dies. An integrated AXI Bridge converts standard AXI protocol signals to the AIB interface, allowing designers to establish die-to-die connectivity while minimizing changes to the existing SoC architecture.

The solution has demonstrated silicon-proven interoperability with Arm NI-700 and Arm NIC-400 interconnects across separate dies, together with efficient 32-bit AXI word transfers.

Its AIB interface supports 40-bit data transfer across 20 DDR data lanes, with data transfers operating from the AXI clock domain and configuration management handled through a lower-speed APB clock domain.

By combining AXI compatibility with an optimized AIB-based architecture, the IP helps semiconductor developers reduce integration complexity while enabling reliable, high-performance communication across advanced chiplet-based platforms.

Key Technical Features

The D2D Interconnect IP Core incorporates a comprehensive set of features for high-performance multi-die semiconductor designs:

• Up to 1.6 Gbps per bump at 800 MHz DDR operation
• Up to 32 Gbps aggregate bandwidth per channel across 20 DDR data lanes
• Approximately 12 ns low-latency operation
• Integrated AXI Bridge supporting Controller and Target configurations
• APB-based configuration and management
• Built-in Error Correction Code (ECC)
• Integrated PRBS self-test capability
• Digital DLL compensation and latency-reduction logic
• Input clock support up to 800 MHz for AXI and 100 MHz for APB
• Operating voltage range of 0.9 V to 1.10 V

Together, these capabilities provide a robust foundation for implementing high-bandwidth, energy-efficient die-to-die connectivity in demanding chiplet and multi-die applications.

Comprehensive Design Deliverables for Faster Integration

The D2D Interconnect IP Core is supplied with a comprehensive set of design deliverables to support integration throughout the semiconductor development flow, from simulation and synthesis through verification, physical implementation, and manufacturing.

The deliverables include:

• Complete product and integration documentation
• Verilog simulation models
• Liberty timing libraries (.lib/.db)
• CTL/CTLDB verification files
• ATPG support files using STIL Procedure Files (SPF)
• Layout Versus Schematic (LVS) verification files (CDL)

These comprehensive deliverables package helps semiconductor companies reduce integration effort, mitigate implementation risk, and accelerate development schedules from initial design through silicon realization.

Availability: This Die-Die IP Core is available for immediate licensing. For more information on licensing options and pricing, please drop a request: contact@t-2-m.com

About T2M: T2M is a global independent semiconductor technology expert, supplying complex semiconductor IP Cores, Software, KGD, and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB, and Satellite SoCs.