T2M Advances RISC-V CPU IP Cores Portfolio for Next-Generation AI and Intelligent Edge SoCs

September 28, 2026 -

Scalable 32-bit and 64-bit RISC-V compute spanning embedded control, functional safety and vector/matrix AI acceleration—backed by a complete software and development ecosystem.

T2M announces the expansion of its RISC-V CPU IP cores portfolio, enabling chip companies to scale from embedded and real-time control to application-class processing and AI acceleration within a flexible RISC-V architecture.

As AI increasingly moves from the cloud to intelligent edge devices, SoC developers need more than a general-purpose CPU. They need the ability to combine scalar processing, vector compute, matrix acceleration and application-specific accelerators while balancing performance, power, area and safety.

T2M's RISC-V portfolio is built around this requirement, offering:

• 32-bit and 64-bit RISC-V CPU IP spanning embedded, real-time and application-class processing
• Single- and multi-core architectures for scalable compute
• RVV 1.0 vector processing, with implementations supporting up to 1024-bit vector width
• Matrix and AI acceleration for compute-intensive edge workloads
• Interfaces for NPU and application-specific accelerator integration
• Functional-safety architectures, including DCLS Split/Lock options
• Configurable cache, tightly integrated memory, MMU, security, debug and trace
• Flexible CPU configuration and customization for differentiated SoCs

The portfolio addresses both ends of the compute spectrum. TAE520 targets high-performance, safety-critical embedded processing with a 6-stage superscalar in-order architecture, up to 5.81 CoreMark/MHz, DCLS Split/Lock functional safety and optional FPU/DSP capabilities.

For AI-oriented SoCs, TDS550 combines a 64-bit RISC-V architecture with RVV 1.0 vector processing and an Attached Matrix Extension (AME), enabling CPU, vector and matrix compute to work together for intelligent-edge workloads such as robotics, intelligent industrial control, smart vision and Edge AI.

The processor IP is complemented by a complete development environment including GCC and LLVM toolchains, IDE and debugging support, GDB, QEMU, SDKs, CPU simulation and FPGA evaluation platforms—allowing software development and architecture validation to begin well before silicon.

For chip companies, this means greater freedom to select and customize the right compute architecture, integrate domain-specific acceleration and develop software earlier—reducing the effort between processor selection and production silicon.

 T2M RISC-V CPU IP Cores— Flexible Compute. AI Ready. Safety Ready. Built for Differentiated Silicon.

About: T2M is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For datasheets, technical specifications, evaluation and licensing inquiries, please drop a request contact@t-2-m.com