Introduction session

• "Impact of the Worldwide Crisis of the IP SoC Business ", Jim Tully, Gartner Dataquest, UK
• "IP/SoC Market", Gabriele Saucier, D&R, France
• "The Role of Standards in Design ", Ian Phillips, ARM,UK
• "Technological Review: Layout Optimization and Design For Manufacturing ", Hein Van Der  Wildt, Sagantec, USA

• " The Challenge of Wireless Integrated Systems " - Ernesto Perea, ST Microelectronics, France
• "Adoption of OPC and the Impact on Design and Layout " - O. Toublan, Mentor Graphics Corp., France
• " Interconnect Parasitics and IP Reuse " - Roberto Suaya, Mentor Graphics, France

IP/SoC Design

• "Application Specific Reconfigurable Core for Dataflow Oriented Computing" - G. Sassatelli, M. Robert, L. Torres, G. Cambon, C. Diou, J. Galy, LIRMM, France.
• "Integrating On-Chip Communications in HW/SW-Partitioning of networking Systems-on-Chip" - T. Wild, J. Foag, N. Pazos, TU Munich, W. Brunnbauer, Infineon, USA
• "Multimedia Processor platform for Mobile Terminals: the importance of design reuse to meet high quality products in a shorter time-to-market." -  Antonio Grassi, Accent (Italy)
• "SoC Derivatives Design Flow : adding Bluetooth Functionality" - P. Bricaud, T. Delaye (France) - Mentor Graphics; M. Eftimakis - Newlogic (France)

IP/SoC Design and Validation
 

• "System-Level Performance Estimation for VLSI Networking-Architectures Methodology " - N. Pazos, W. Brunnbauer, J. Foag, T. Wild - LIS-TUM, Germany, Infineon, USA
• "Intranet Based IP Supply Chain for SoC Design" - B. Missaoui, K. Skiba, L. Ghanmi, D&R, INPG, France
• "VSIA VC Quality DWG Report" , - Pierre Bricaud, Mentor Graphics, France
• "A digital high-speed serial link core for chip-to-chip data transmission" Daniel Mayer, Tachys Technologies, France
• "A mixed signal Codec, latest heir of a highly qualified family, shrink-wrapped with its complete SoCKET" Ann Magiorani, Dolphin Integration, France
• "TransEDA IP Quality Alliance Program - TransEDA Verification Solutions" - François Durif, TransEDA , France

• "E-Design Concepts and Practice: An Overview" - Dr. Franc Brglez, Computer Science Dept., NC State University, USA
• "IP XML Encapsulation Portal" - M.Hamdoun, A.Ghrab, P.Hernandez, G.Saucier,  D&R, INPG, France

Verification Methodology and Platform

• "Equivalence Checking SoC Custom Blocks " - S. Napper, Innologic Systems Inc., USA
• "FPGA-based prototyping techniques: a roadmap" - Marco Pavesi, Italtel, Italy
• "A "Meet-in-the-middle" Verification Strategy" -  Huy Nam Nguyen, Bull, France
• "imPROVE-HDL: A New Model Checker Used in an Industrial Environment " -  Imed Moussa and Samuel Dellacherie, TNI-Valiosys, France
• "Leveraging Functional Verification IP"  Andrew Betts, Qualis Europe

Panel : IP and Technology Issues

Moderator :
- Tim Daniels, LSI Logic, UK

Panelists :
- Massimo Vanzi, Accent, Italy
- Yannick Duquesne, MIPS Technologies, France
- Hein Van Der  Wildt, Sagantec, USA

Panel : IP Exchange and e-Design

Moderator:
- Ian Phillips, ARM, UK

Panelists:
- Thierry Pfirsch, Alcatel, Belgium
- Franc Brglez, Computer Science Dept. , NC State University, USA
- Andreas Bruening, Sci-worx, Germany
- Gabriele Saucier, D&R, France

Panel : Design and Verification of SoC's : Prototyping Platforms Challenges

Moderator :
- Michel Robert, LIRMM, France

Panelists :
- Dr. Luc Burgun, EV Engineering, France
- Marco Pavesi, Italtel, Italy
- Carlos SERRA, ST Microelectronics, France
- James McLenaghan, Xilinx, France