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EVE today announced immediate availability of a 10-Gigabit Ethernet (10GbE) validation platform for its ZeBu (Zero Bugs) family of system-on-chip (SoC) hardware-assisted verification platforms.
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Cadence today launched the industry’s first IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard, an interface technology used in the rapidly growing solid-state drive (SSD) market. The solution includes Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem.
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CEVA today announced that it has been ranked by leading research firm The Linley Group as the worldwide leader in DSP IP shipments in 2011, with a 90% market share. The market share numbers were published in The Linley Group’s recent report, titled ‘A Guide to CPU Cores and Processor IP’.
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MIPS Technologies today introduced a new generation of microprocessor cores. The Aptiv Generation cores, including the proAptiv, interAptiv and microAptiv families, offer three distinct performance levels for applications across MIPS' target segments.
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Evatronix SA has announced the release of the first member of its PANTA high performance display controller core family. Developed using ARM technology the PANTA DP20 is targeted specifically at high-end mobile/portable products, like smartphones and tablet PCs, with ultra-low power consumption that does not sacrifice processing performance.