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Updated: Tue, 18 Jun 2013 01:00:02 +0200
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How to calculate CPU utilization How to calculate CPU utilization |
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Dynamic Memory Allocation and Fragmentation in C and C++ In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynamic memory can be problematic and inefficient. For desktop applications, where memory is freely available, these difficulties can be ignored. For embedded - generally real time - applications, ignoring the issues is not an option. |
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FPGA programming step by step FPGA programming step by step |
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4 | 3 |
Understanding cascaded integrator-comb filters Understanding cascaded integrator-comb filters |
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Creating highly reliable FPGA designs In this article, Angela Sutton of Synopsys explains how design teams can use automated features within Synopsys’ Synplify design solution to protect their FPGA designs from soft errors. |
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6 | 14 |
FPGA Implementation of AES Encryption and Decryption This paper presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) which has been selected as New Algorithm by the National Institutes of Stand |
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7 | New!!! |
Low Power Design for Testability Design for testability (DFT) and low power issues are very much related with each other. In this paper power reduction methodologies are discussed for a given design. Power management circuitries are developed to reduce functional power of the design. Power aware Scan Chains are implemented to create test environment which result into reduction in test power. Design for testability is applied to test power management circuits using Power Test Access Mechanism. Also few methods are discussed to implement DFT to test power management circuitry and improve test and fault coverage during ATPG. |
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Adaptive Frequency Hopping for Reduced Interference between Bluetooth® and Wireless LAN Adaptive Frequency Hopping for Reduced Interference between Bluetooth® and Wireless LAN |
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The ARM Cortex-A9 Processors This whitepaper describes the details of a newly developed processor design within the common ARM Cortex applications profile |
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10 | 6 |
NAND Flash memory in embedded systems This paper presents fundamental information about NAND Flash memory used in Embedded Systems. It discusses various aspects of this storage media such as interface, architecture, error source and error correction as well as software required for building application. |
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CORTEX-R versus CORTEX-M Cortex-R and cortex-M series is targeted for different requirements and for different applications. It is important to know the parameters and features that separates them as there could be applications where both of them can fit in. This paper is targeted for such a scenario and helps the Designers for selection. The final objective is to help the Designers or Developers to have understanding of Architectures of ARM. |
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12 | 5 |
MIPI™ MPHY - An introduction Recognizing the need for high bandwidth pipes, the MIPI alliance has been defining standards for these serial interfaces. D-PHY, which was ratified 1.5 years ago but with a near final version for 3 years, supports 1Gbps per lane. The M-PHY specification, whose 1.0 version is about to be ratified, supports about 1.25Gbps/1.5Gbps and has options to support 2.5Gbps/3Gbps and 5Gbps/6Gbps per lane. |
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13 | 19 |
Cortex-M And Classical Series ARM Architecture Comparisons ARM has introduced many processors. Each set or groups of processors are having different core and different Features. A new entrant or Designer to the ARM can make use of this paper for easy understanding and choose a processor that is well suited for the requirements. This paper gives brief comparison of the Architectures. |
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Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects by Jerry C. Chen -- Genesys Logic America, Inc. |
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15 | New!!! |
Functional Safety Certification for Subsystem Developers The rise of highly-automated systems in transportation and manufacturing has caused a profound change in the philosophy of system design. Increasing automation has shifted the responsibility for the safety of humans and property from the machine operator to the machine builders. This responsibility, and the processes and systems necessary to fulfill it, have become known collectively as functional safety. |
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16 | New!!! |
H.264 High Profile: Codec for Broadcast & Professional Video Application High definition video content is becoming rampant as more and more countries are now transitioning into digital life. The ways to deliverHigh definition content in a bandwidth limited channel have become challenge in itself. To cater to such highly demanding broadcast & professional video markets, we require a compression / decompression standard that allows no compromise on the quality of the video that has to be broadcasted over a bandwidth constrained networks. |
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17 | New!!! |
Power analysis of clock gating at RTL In this article, we will discuss the use of clock gating techniques with design examples for achieving lower power and also highlight the impact of clock gating on different areas of the design process like metastability with clock domain crossings and testability. The article also details the do's and don'ts of clock gating to avoid chip failures and unnecessary power dissipation. |
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18 | New!!! |
Using non-volatile memory IP in system on chip designs While unlimited re-programmability might be seen as an advantage during software development, once the device is shipped it becomes a product’s greatest vulnerability... |
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19 | New!!! |
Functional Finite State Machine Paths Coverage using SystemVerilog There are several efforts to solve the problem of modeling FSM coverage. In this paper, we present two new methods to implement the recording of FSM coverage into the functional coverage model in a constrained random coverage-driven verification environment. These methods enable state machine coverage data implementation, interpretation, and analysis across the multi- abstraction levels from TLM, to gate level. |
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Comparing AMBA AHB to AXI Bus using System Modeling This paper discusses the construction of an AMBA Advanced High-performance Bus (AHB) Shared Bus and AMBA Advanced eXtensible Interface (AXI) point-to-point Bus using a graphical modeling environment that achieved approximately 95% cycle accuracy. |
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