 |
|
| |
Headline (Last 30 Days) Sign Up for SoC News Alert  |
|
 | |
| | |
| | |
| Articles for the Week of Mar. 18, 2010 | |
| | |
| | |
Featured Article
Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment The paper describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM model for high speed simulation, early software development and early test-bench creation. |
|
| Additional Articles | |
| | |
| | |
| Articles for the Week of Mar. 11, 2010 | |
| | |
| | |
Featured Article
Initial Investigations into UML Based Architectural Reference Patterns for Set-Top Boxes This paper analyses a leading-edge Set-top Box (STB) design for architecture reference patterns. Specifically, the following contributions are made: (i) identifying and documenting (in UML) STB architectural reference patterns, and (ii) providing empirical (quantitative) analysis of pattern use. |
|
| Additional Articles | |
| | |
| | |
| Articles for the Week of Mar. 04, 2010 | |
| | |
| | |
Featured Article
Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nmBecause the dimensions of lithography are now closer to the fundamental physical limits, scaling is more and more difficult and thus multi-core processor solutions are just starting to be more popular in the embedded area. This paper describes in details the features that allow SoCs to be built with up to eight 1.6 GHz PowerPC CPU cores in an embedded system supporting Symmetric Multiprocessing (SMP) architecture. The balancing between CPU execution speed, memory bandwidth and latency, and coherency overhead has been the objective of the design of the PLB6 and the L2 Cache IP's, to reduce as much as possible the drop-off in performance-per-core inherent in an SMP approach. |
|
| Additional Articles | |
| | |
| | |
| Articles for the Week of Feb. 25, 2010 | |
| | |
| | |
Featured Article
Hardware Solutions to the Challenges of Multimedia IP Functional VerificationThis paper discusses the functional verification of IP cores and problems which arise during their implemenation in today’s advanced applications. First, the usual approach to functional verification is presented together with its common difficulties. The next part features an example of hardware verification environment which was used for verification of the Evatronix JPEG 2000 encoder multimedia IP core in order to illustrate this paper’s thesis. After a short description of the JPEG 2000 image compression algorithm, the structure of the environment is presented. Then the manner of test cases preparation is described as well as criteria used to determine whether a particular test is passed or failed. Finally, numerical results of hardware verification experiment are presented with some comments which conclude the paper. |
|
| © 2010 Design And Reuse All Rights Reserved. No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse. Read our privacy guidelines. Contact us. |
 |
|
|
|