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EETimes

 
 Introduction session

Impact of New Technologies on IP Reuse. From Silicon to System Level  Concerns.
 


IP/SoC Design


IP/SoC Design and Validation
 

IP Exchange and e-Design


Verification Methodology and Platform


Panel : IP and Technology Issues

Moderator :
- Tim Daniels, LSI Logic, UK

Panelists :
- Massimo Vanzi, Accent, Italy
- Yannick Duquesne, MIPS Technologies, France
- Hein Van Der  Wildt, Sagantec, USA


Panel : IP Exchange and e-Design

Moderator:
- Ian Phillips, ARM, UK

Panelists:
- Thierry Pfirsch, Alcatel, Belgium
- Franc Brglez, Computer Science Dept. , NC State University, USA
- Andreas Bruening, Sci-worx, Germany
- Gabriele Saucier, D&R, France


Panel : Design and Verification of SoC's : Prototyping Platforms Challenges

Moderator :
- Michel Robert, LIRMM, France

Panelists :
- Dr. Luc Burgun, EV Engineering, France
- Marco Pavesi, Italtel, Italy
- Carlos SERRA, ST Microelectronics, France
- James McLenaghan, Xilinx, France