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Introduction session
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"Impact of the Worldwide Crisis of the IP SoC Business ", Jim Tully, Gartner
Dataquest, UK
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"IP/SoC Market", Gabriele Saucier,
D&R, France
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"The Role of Standards in Design ", Ian Phillips, ARM,UK
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"Technological Review: Layout Optimization
and Design For Manufacturing ", Hein Van Der Wildt, Sagantec,
USA
Impact of New Technologies on IP Reuse. From Silicon to System Level
Concerns.
IP/SoC Design
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"Application Specific Reconfigurable Core
for Dataflow Oriented Computing" - G. Sassatelli, M. Robert, L. Torres,
G. Cambon, C. Diou, J. Galy, LIRMM, France.
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"Integrating On-Chip Communications in
HW/SW-Partitioning of networking Systems-on-Chip" - T. Wild, J. Foag,
N. Pazos, TU Munich, W. Brunnbauer, Infineon, USA
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"Multimedia Processor platform for Mobile
Terminals: the importance of design reuse to meet high quality products
in a shorter time-to-market." - Antonio Grassi, Accent (Italy)
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"SoC Derivatives Design Flow : adding
Bluetooth Functionality" - P. Bricaud, T. Delaye (France) - Mentor
Graphics; M. Eftimakis - Newlogic (France)
IP/SoC Design and Validation
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"System-Level Performance Estimation for
VLSI Networking-Architectures Methodology " - N. Pazos, W. Brunnbauer,
J. Foag, T. Wild - LIS-TUM, Germany, Infineon, USA
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"Intranet Based IP Supply Chain for SoC
Design" - B. Missaoui, K. Skiba, L. Ghanmi, D&R, INPG, France
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"VSIA VC Quality DWG Report" , - Pierre Bricaud, Mentor Graphics, France
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"A digital high-speed serial link core for chip-to-chip data transmission"
Daniel Mayer, Tachys Technologies, France
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"A mixed signal Codec, latest heir of
a highly qualified family, shrink-wrapped with its complete SoCKET"
Ann Magiorani, Dolphin Integration, France
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"TransEDA IP Quality Alliance Program
- TransEDA Verification Solutions" - François Durif, TransEDA
, France
IP Exchange and e-Design
Verification Methodology and Platform
Panel : IP and Technology Issues
Moderator :
- Tim Daniels, LSI Logic, UK
Panelists :
- Massimo Vanzi, Accent, Italy
- Yannick Duquesne, MIPS Technologies, France
- Hein Van Der Wildt, Sagantec, USA
Panel : IP Exchange and e-Design
Moderator:
- Ian Phillips, ARM, UK
Panelists:
- Thierry Pfirsch, Alcatel, Belgium
- Franc Brglez, Computer Science
Dept. , NC State University, USA
- Andreas Bruening, Sci-worx,
Germany
- Gabriele Saucier, D&R, France
Panel : Design and Verification of SoC's : Prototyping Platforms
Challenges
Moderator :
- Michel Robert, LIRMM, France
Panelists :
- Dr. Luc Burgun, EV Engineering,
France
- Marco Pavesi, Italtel, Italy
- Carlos SERRA, ST Microelectronics, France
- James McLenaghan, Xilinx, France
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