Design & Reuse
Catalog of SIP Cores
System on Chip design resources
2025 IP
601
4.0
SATA Device ADCI Core
IntelliProp’s SATA™ Device ADCI IP core (IPC-SA155A-DT) is a high-performance, industry-standard Serial-ATA device interface engine designed to enable...
602
4.0
SATA Host AHCI Core
The IntelliProp SATA Host AHCI (IPC-SA156A-HI) is an industry standard Serial-ATA (SATA) host interface core that enables customers to use high throug...
603
4.0
SATA Host App Core
IntelliProp’s SATA Host App Core (IPC-SA101A-HI) is a silicon-proven, industry-standard Serial-ATA (SATA) host interface IP designed to eliminate stor...
604
4.0
SATA RAID Core
The IntelliProp IPC-BL109A-RD SATA RAID Core is a hardware design block written in HDL that performs RAID 0 operations to provide higher performance a...
605
4.0
SATA™ "Y" Bridge with RAID IP Core
IntelliProp’s SATA™ "Y" Bridge with RAID IP Core (IPP-SA112A-BR) is a production-hardened, high-availability storage solution engineered to allow two ...
606
4.0
Gen-Z Link Layer IP Core
The IntelliProp IPC-GZ198A-ZM Gen-Z Link Layer is an IP Core that allows companies to build Gen-Z compliant devices. The IPC-GZ198A-ZM is compliant wi...
607
4.0
Gen-Z Physical Layer for 802.3 IP Core
The IntelliProp IPC-GZ196A-ZM Gen-Z Physical Layer for 802.3 is an IP Core that allows companies to attach a Gen-Z core to an 802.3 Phy. The IPC-GZ196...
608
4.0
Gen-Z Physical Layer for PCIe IP Core
The IntelliProp IPC-GZ197A-ZM Gen-Z Physical Layer for PCIe is an IP Core that allows companies to attach a Gen-Z core to a PCIe Phy. The IPC-GZ197A-Z...
609
4.0
Gen-Z Requester IP Core
The IntelliProp IPC-GZ190A-HI Gen-Z Requester is an IP Core that allows companies to build Gen-Z compliant Requester devices. The IPC-GZ190A-HI is com...
610
4.0
Gen-Z Responder IP Core
The IntelliProp IPC-GZ189A-DT Gen-Z Responder is an IP Core that allows the building of Gen-Z compliant media devices. The IPC-GZ189A-DT is compliant ...
611
4.0
Gen-Z Switch IP Core
The IntelliProp IPC-GZ201A-ZM Gen-Z Switch is an IP Core that allows companies to build Gen-Z compliant components. The IPC-GZ201A-ZM is compliant wit...
612
4.0
USB 3.0 Hub
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613
4.0
USB3.1 PHY
With sophisticated architecture and advanced technology, KNiulink USB3.1 transceiver IP with PMA and PCS layer is designed for low power and high perf...
614
4.0
NVMe-to-SATA Bridge
The IntelliProp IPP-NV186A-BR is an NVMe-to-SATA Bridge that utilizes the IntelliProp NVMe Target IP Core and the IntelliProp SATA AHCI Host Core to c...
615
3.0
I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a t...
616
3.0
I2C Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a t...
617
3.0
I2C Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...
618
3.0
I2C Slave Controller - Low Power, Low Noise Config of User Registers
The DB-I2C-S-SCL-CLK is an I2C Slave Controller IP Core focused on low power, low noise ASIC / ASSP designs requiring the configuration & control of r...
619
3.0
I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)
The Digital Blocks DB-I2C-S-APB / DB-I2C-S-AHB / DB-I2C-S-AXI / DB-I2C-S-AVLN Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC,NIOS II or othe...
620
3.0
2D Graphics Hardware Accelerator (AXI4 Bus)
The DB9200AXI4 2D Graphics Engine Verilog IP Core targets low VLSI footprint, high-performance hardware accelerated graphics applications. The DB92...
621
3.0
AHB2APB Bridge IP
Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...
622
3.0
UHS-II PHY for SD4/SD5 TSMC 12nm FF
SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...
623
3.0
UHS-II PHY for SD4/SD5 TSMC 16nm FF
SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...
624
3.0
MIPI D-PHY NEC 90nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
625
3.0
MIPI M-PHY Designed For GF 28nm
ACS-AIP-MPHY-28HK MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A ...
626
3.0
MIPI PHY
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications. It is designed for low power and high-performance application. Th...
627
3.0
Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO
The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bu...
628
3.0
USB 3.0 Device
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629
2.5
SATA 3 Host Controller on ARRIA V FPGA
The LDS SATA 3 HOST AR5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Stratix IV GX FPGA. T...
630
2.5
SATA 3 Host Controller on ZYNQ
The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS SATA 3 HOST...
631
2.5
SATA 3 HOST IP on ARRIA 10 FPGA
The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The L...
632
2.5
SATA Device Controller on Kintex 7
The LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The LDS SATA...
633
2.5
SATA HOST 3 ON KINTEX 7 Ultrascale
The LDS SATA 3 HOST XK7U IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 Ultrascale speed grade 2 FPGA. The...
634
2.5
SATA HOST 3 ON VIRTEX 7 GTH
...
635
2.5
SATA Host 6G Controller on Kintex 7
The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The LDS SATA 3 ...
636
2.5
SATA Host on Xilinx Zynq Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS SATA 3 H...
637
2.5
LDS SATA RECORDER IP ON ARTIX 7
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638
2.5
LDS SATA RECORDER ON ZYNQ
...
639
2.5
Xilinx Ultra Scale Plus SATA HOST IP
The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_...
640
2.5
Virtex 7 GTX SATA 3 Host Controller
The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed grade 2 FPGA. The LDS SA...
641
2.5
DSC 1.2b Decoder
The DSC 1.2b Decoder is an efficient video decompression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for ...
642
2.5
DSC 1.2b Encoder
The DSC 1.2b Encoder is an efficient video compression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for lo...
643
2.5
ZYNQ SATA 3 AHCI Host Controller with Linux Driver
The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed gr...
644
2.0
I2C Master Serial Interface Controller
Master serial interface compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be c...
645
2.0
I2C Slave Serial Interface Controller
Slave serial interface compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your FPGA, CPLD or ASIC device. ...
646
2.0
I3C Dual Controller
The Arasan I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Seconda...
647
2.0
56G SerDes Ethernet
56G SerDes IP core supports PAM4 signaling in the range of 25.0-60.0 Gbps using full-rate and half-rate modes with scrambled data. Non-return-to-zero ...
648
2.0
UART to I2C Bridge Controller
Allows simple connectivity between a UART 2-wire port (Tx/Rx) and an I2C compatible bus. Allows simple programming and debug of an I2C device using a ...
649
2.0
SATA 3 Host Controller on Xilinx Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS_SATA3_HO...
650
2.0
LDS SATA RECORDER ON KINTEX 7
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