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30 IP
1
31.0
GDDR7 VIP
SmartDV's GDDR7 Verification IP is a comprehensive solution for verifying Graphics Double Data Rate 7 memory interfaces, the first JEDEC graphics DRAM...
2
31.0
DDR6 VIP
SmartDV's DDR6 Verification IP is a comprehensive early-access solution for verifying next-generation DDR6 SDRAM memory interfaces, enabling design an...
3
30.0
DDR4 Verification IP
Truechip's DDR4 Verification IP provides an effective & efficient way to verify the components interfacing with DDR4 interface of an ASIC/FPGA or SoC....
4
21.0
DDR5 (DIMM + NVRAM + DFI) VIP
SmartDV's DDR5 Verification IP is a comprehensive solution for verifying DDR5 SDRAM memory interfaces across device, non-volatile RAM, DIMM module, an...
5
11.0
DDR4 (3DS + DIMM + DB + RCD + DFI) VIP
SmartDV's DDR4 Verification IP is a comprehensive solution for verifying DDR4 SDRAM memory interfaces across device, 3D Stacked, DIMM module, Data Buf...
6
0.0
VC Verification IP for DDR5
Synopsys® VC Verification IP for JEDEC DDR5, deployed in November 2016, provides a comprehensive set of protocol, methodology, verification, and produ...
7
0.0
GDDR5/5x VIP
SmartDV's GDDR5/5X Verification IP is a comprehensive solution for verifying Graphics Double Data Rate memory interfaces for high-bandwidth GPU, AI ac...
8
0.0
GDDR6 VIP
SmartDV's GDDR6 Verification IP is a comprehensive solution for verifying Graphics Double Data Rate 6 memory interfaces for high-bandwidth GPU, AI acc...
9
0.0
DDR2 SDRAM VIP
Double-Data-Rate-Two Synchronous Dynamic Random Access Memory (DDR2 SDRAM) is the memory technology used for high speed data transfer. This class of m...
10
0.0
DDR3 (3DS + DIMM + DFI) VIP
SmartDV's DDR3 Verification IP is a comprehensive solution for verifying DDR3 SDRAM memory interfaces across device, DIMM, 3D Stacked, and PHY interfa...
11
0.0
DDR3 Verification IP
Truechip's DDR3 Verification IP provides an effective & efficient way to verify the components interfacing with DDR3 interface of an ASIC/FPGA or SoC....
12
0.0
Verification IP for DDR3 (UDIMM, RDIMM, LDIMM)
...
13
0.0
Verification IP for DDR3 (UDIMM, RDIMM, LDIMM)
Synopsys® VC VerificationIP for the JEDEC DDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and p...
14
0.0
Simulation VIP for DDR4
In production since 2011 on dozens of production designs....
15
0.0
Simulation VIP for DDR4 LRDIMM
First to market with full DDR4 LRDIMM support....
16
0.0
Simulation VIP for DDR5
In production since 2014 on dozens of production designs....
17
0.0
Simulation VIP for DDR5 DIMM
First to market with full DDR5 DIMM support....
18
0.0
Simulation VIP for DFI
Complete solution for extensive and fast verification used by multiple production designs....
19
0.0
Simulation VIP for GDDR6
Sign-off model for dozens of production designs....
20
0.0
Simulation VIP for HBM
In production since 2015 on dozens of production designs....
21
0.0
Simulation VIP for HBM3
First to market with multiple early adopters of production designs....
22
0.0
Simulation VIP for HyperFlash
Hyperflash in production since 2018 for many production designs....
23
0.0
Simulation VIP for HyperRam
HyperRam in production since 2018 for many production designs....
24
0.0
Simulation VIP for LPDDR4
In production since 2015 on dozens of production designs....
25
0.0
Simulation VIP for LPDDR5
In production since 2015 on dozens of production designs....
26
0.0
Simulation VIP for OctaRam
In production since 2018 for many production designs....
27
0.0
Simulation VIP for ONFi
In production since 2011 for dozens of production designs....
28
0.0
Simulation VIP for OSPI NOR
In production since 2012 for dozens of designs....
29
0.0
DRAM Memory Model - Synthesizable
Synthesizable DRAM Model of GDDR5,GDDR6 & DDR4 for emulation platform / test chip development and memory controller performance measurement. ...
30
0.0
Synopsys Verification IP for DDR4 (UDIMM, RDIMM, LDIMM)
Synopsys® VC VerificationIP for the JEDEC DDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and p...
