Design & Reuse
Catalog of SIP Cores
System on Chip design resources
7 IP
1
0.0
UART (interface) eVC
The Universal Asynchronous Receiver Transmitter (UART) interface-level eVC is a powerful verification bundle built around the UART inteface industry s...
2
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UART 16x50 eVC
The Universal Asynchronous Receiver Transmitter (UART) 16x50 device-level eVC is a powerful verification bundle built around the UART 16x50 class of d...
3
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UART eVC - Fully documented, of the shelf component for Verisity's Specmean Elite functional verification environment
Silicon Interfaces’ UART eVC is a fully documented, off the shelf component for Verisity’s Specman EliteTM functional verification environment. At the...
4
0.0
UART VMM based Verification IP
The VMM based UART VIP is complaint to National Semiconductor 16550 design. The UART interface allows a duplex, asynchronous, serial communication and...
5
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UART/USART VIP
SmartDV's UART/USART Verification IP is a comprehensive solution for verifying Universal Asynchronous and Synchronous/Asynchronous Receiver/Transmitte...
6
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VC Verification IP for UART
Synopsys VC Verification IP (VIP) for UART provides a comprehensive set of protocol, methodology, verification and productivity features, enabling use...
7
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Simulation VIP for UART
Best-in-class UART Verification IP for your IP, SoC and system-level design testing. In production since 2014 on dozens of production designs....