Design & Reuse
Catalog of SIP Cores
System on Chip design resources
11 IP
1
31.0
LPDDR6 with DFI VIP
SmartDV's LPDDR6 Verification IP is a comprehensive solution for verifying the next-generation Low Power Double Data Rate 6 memory interface, the firs...
2
21.0
LPDDR5/5x with DFI VIP
SmartDV's LPDDR5/5X Verification IP is a comprehensive solution for verifying Low Power Double Data Rate 5 and LPDDR5X memory interfaces across device...
3
0.0
LPDDR3 Verification IP
Truechip's LPDDR3 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR3 interface of an ASIC/FPGA or ...
4
0.0
LPDDR3 VIP
SmartDV's LPDDR3 Verification IP is a comprehensive solution for verifying Low Power Double Data Rate 3 memory interfaces, the high-bandwidth, power-e...
5
0.0
LPDDR4 Verification IP
Truechip's LPDDR4 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR4 interface of an ASIC/FPGA or ...
6
0.0
LPDDR4/4x with DFI VIP
SmartDV's LPDDR4/4X Verification IP is a comprehensive solution for verifying Low Power Double Data Rate 4 and LPDDR4X memory interfaces across device...
7
0.0
LPDDR5 Verification IP
Truechip's LPDDR5 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR5 interface of an ASIC/FPGA or ...
8
0.0
Synopsys Verification IP for LPDDR2
...
9
0.0
Synopsys Verification IP for LPDDR2
Synopsys® VC Verification IP for the JEDEC LPDDR2 memory protocol specification provides a comprehensive set of protocol, methodology, verification an...
10
0.0
Synopsys Verification IP for LPDDR3
Synopsys® VC VerificationIP for the JEDEC LPDDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and...
11
0.0
Synopsys Verification IP for LPDDR4
Synopsys® VC Verification IP for the JEDEC LPDDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification an...