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57 IP
51
0.0
Simulation VIP for LPDDR4
In production since 2015 on dozens of production designs....
52
0.0
Simulation VIP for LPDDR5
In production since 2015 on dozens of production designs....
53
0.0
Simulation VIP for OctaRam
In production since 2018 for many production designs....
54
0.0
Simulation VIP for ONFi
In production since 2011 for dozens of production designs....
55
0.0
Simulation VIP for OSPI NOR
In production since 2012 for dozens of designs....
56
0.0
DRAM Memory Model - Synthesizable
Synthesizable DRAM Model of GDDR5,GDDR6 & DDR4 for emulation platform / test chip development and memory controller performance measurement. ...
57
0.0
Synopsys Verification IP for DDR4 (UDIMM, RDIMM, LDIMM)
Synopsys® VC VerificationIP for the JEDEC DDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and p...