Design & Reuse
258 IP
251
0.0
NVDIMM-P Memory Model
NVDIMM P Memory Model provides an smart way to verify the NVDIMM P component of a SOC or a ASIC. The SmartDV s NVDIMM P memory model is fully complian...
252
0.0
SWD (Serial Wire Debug) Verification IP
SWD(Serial Wire Debug) Verification IP provides an efficient and simple way to debug and trace functionality on processor cores and System on Chip (So...
253
0.0
Twin Quad NOR Flash Memory Model
Twin Quad NOR Flash Memory Model provides an smart way to verify the Twin Quad NOR Flash component of a SOC or a ASIC. The SmartDV s Twin Quad NOR Fla...
254
0.0
SWP (Single Wire Protocol) Verification IP
SWP Verification IP is a smart way to verify the SWP component of a SOC or ASIC. The SmartDV s SWP Verification IP is fully compliant with standard ET...
255
0.0
Excelon FRAM Memory Model
Excelon FRAM Memory Model provides an smart way to verify the Excelon FRAM component of a SOC or a ASIC. The SmartDV s Excelon FRAM memory model is fu...
256
0.0
CXS a/b Verification IP
Truechip's CXS Verification IP provides an effective & efficient way to verify CXS ON Chip or OFF Chip interface. Truechip's CXS VIP is fully complian...
257
0.0
HyperFlash Memory Model
HyperFlash Memory Model provides an smart way to verify the HyperFlash component of a SOC or a ASIC. The SmartDV s HyperFlash memory model is fully co...
258
0.0
HyperRAM Memory Model
HyperRAM Memory Model provides an smart way to verify the HyperRAM component of a SOC or a ASIC. The SmartDV s HyperRAM memory model is fully complian...