Design & Reuse
Catalog of SIP Cores
System on Chip design resources
608 IP
601
0.0
Synopsys Verification IP for DDR4 (UDIMM, RDIMM, LDIMM)
Synopsys® VC VerificationIP for the JEDEC DDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and p...
602
0.0
Synopsys Verification IP for LPDDR2
...
603
0.0
Synopsys Verification IP for LPDDR2
Synopsys® VC Verification IP for the JEDEC LPDDR2 memory protocol specification provides a comprehensive set of protocol, methodology, verification an...
604
0.0
Synopsys Verification IP for LPDDR3
Synopsys® VC VerificationIP for the JEDEC LPDDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and...
605
0.0
Synopsys Verification IP for LPDDR4
Synopsys® VC Verification IP for the JEDEC LPDDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification an...
606
0.0
Synopsys Verification IP for UniPro
Synopsys® VC Verification IP for the MIPI Alliance UniPro protocol specification provides a comprehensive set of protocol, methodology, verification a...
607
0.0
HyperFlash Memory Model
HyperFlash Memory Model provides an smart way to verify the HyperFlash component of a SOC or a ASIC. The SmartDV s HyperFlash memory model is fully co...
608
0.0
HyperRAM Memory Model
HyperRAM Memory Model provides an smart way to verify the HyperRAM component of a SOC or a ASIC. The SmartDV s HyperRAM memory model is fully complian...