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467 IP
451
0.0
AVSBus v2.1 Verification IP
Truechip's AVSBus Verification IP provides an effective and efficient way to verify the components interfacing with AVSBus interface of an IP and SOC....
452
0.0
SWD (Serial Wire Debug) VIP
SmartDV's SWD Verification IP is a comprehensive solution for verifying the ARM Serial Wire Debug interface, the two-pin low-pin-count alternative to ...
453
0.0
SWI3S v1.0
Truechip's SWI3S Verification IP provides an effective and efficient way to verify the components interfacing with SWI3S interface of an IP and SOC. T...
454
0.0
SWP VIP
SmartDV's SWP Verification IP is a comprehensive solution for verifying the Single Wire Protocol, the ETSI bit-oriented, point-to-point communication ...
455
0.0
AXI3/AXI4 Verification IP
...
456
0.0
CXL 3.0 Verification IP
Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP or SoC....
457
0.0
CXL Switch Verification IP
Truechip's CXL Switch Verification IP provides an effective & efficient way to verify the components interfacing with CXL Switch interface of an IP or...
458
0.0
CXS a/b Verification IP
Truechip's CXS Verification IP provides an effective & efficient way to verify CXS ON Chip or OFF Chip interface. Truechip's CXS VIP is fully complian...
459
0.0
Hybrid Memory Cube (HMC) Verification IP
HMC : Asiczen’s Verification IP for HMC provides a comprehensive set of protocol, methodology, verification and productivity features, enabling user t...
460
0.0
Hybrid Memory Cube Verification IP
Atria Logic Hybrid Memory Cube verification IP is a reusable, configurable verification component developed using SystemVerilog. The IP offers an easy...
461
0.0
Synopsys Verification IP for DDR4 (UDIMM, RDIMM, LDIMM)
Synopsys® VC VerificationIP for the JEDEC DDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and p...
462
0.0
Synopsys Verification IP for LPDDR2
...
463
0.0
Synopsys Verification IP for LPDDR2
Synopsys® VC Verification IP for the JEDEC LPDDR2 memory protocol specification provides a comprehensive set of protocol, methodology, verification an...
464
0.0
Synopsys Verification IP for LPDDR3
Synopsys® VC VerificationIP for the JEDEC LPDDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and...
465
0.0
Synopsys Verification IP for LPDDR4
Synopsys® VC Verification IP for the JEDEC LPDDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification an...
466
0.0
Synopsys Verification IP for UniPro
Synopsys® VC Verification IP for the MIPI Alliance UniPro protocol specification provides a comprehensive set of protocol, methodology, verification a...
467
0.0
HyperBus VIP
SmartDV's HyperBus Verification IP is a comprehensive solution for verifying the HyperBus low signal count, high-performance DDR bus interface for con...
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