CAST Introduces 100 Gbps TCP/IP Hardware Stack IP Core for High-Performance ASIC and FPGA Designs

Autonomous hardware TCP/IP stack delivers reliable, high-throughput, low-latency networking for AI and HPC clusters, hyperscale data centers, SmartNICs, and NVMe-over-TCP systems

Woodcliff Lake, NJ — Semiconductor intellectual property provider CAST today announced the TCPIP-100G Hardware Stack IP core, a complete hardware TCP/IP protocol stack that lets ASIC and FPGA developers add reliable, connection-oriented networking at speeds up to 100 Gbps directly into their own devices with or without a host processor.

The TCPIP-100G core implements a complete TCP/IP hardware protocol stack capable of transmitting and receiving data at speeds up to 100 Gbps. More capable than many offloading engines, it connects systems to an Internet Protocol (IP) network and exchanges data using the TCP protocol without requiring assistance from or even the presence of a host processor. The result is a lean, efficient networking solution for SoC, ASIC, and FPGA developers building products that demand very high throughput, low latency, and low power.

Acting as either a server or a client, the core autonomously opens, maintains, and closes TCP connections without host-system assistance. The integrating system configures network parameters through the core's control registers and then simply streams data in and out, while connection establishment, retransmission, and flow and congestion control are all handled in hardware.

“System designers are moving more data through their silicon than ever, and reliable TCP connectivity at these rates has traditionally meant a heavy software burden or a dedicated CPU,” said Dr. Calliope-Louisa Sotiropoulou, networking product manager at CAST. “Our TCPIP-100G core runs the entire TCP stack in hardware, so SoC teams get extremely high-speed and dependable networking with the configurability and scalability that next-generation systems require.”

Massive Scalability and a Complete Set of Network Functions

The TCPIP-100G core supports up to 32,768 simultaneous TCP sessions, configurable at synthesis time for everything from compact endpoints to high-density data-server applications. It provides the network functions needed for robust deployment, including IPv4, ARP with cache, ICMP (ping reply), VLAN (IEEE 802.1Q) tagging, checksum generation and validation, and Jumbo and Super Jumbo frame support.

Optional features extend the core further: a DHCP client for automatic IP-address assignment, out-of-order TCP packet reassembly, and a full UDP hardware stack with multicast support (IGMPv3). Non-TCP/UDP IP traffic can optionally be forwarded to the system through a dedicated port.

Flexible Processing and Straightforward SoC Integration

Designers can select the packet-processing mode that fits their system. Cut-through mode delivers payload data with the lowest possible latency and minimal memory use, while store-and-forward mode always delivers verified, in-order packets. A wide range of run-time programmable options — including local MAC and IP addresses, port and address filters, retransmission behavior, window sizes, and MSS — lets a single configuration adapt to diverse applications.

The core uses standardized AMBA® interfaces: a 512-bit AXI4-Stream for packet data, a 32-bit AXI4-Lite (or optional APB3) for control and status, and a 2048-bit AXI4 for external memory, with separate clock domains for packet processing and register access. It is independent of the external memory type and controller and of the Ethernet MAC or PHY and can be optionally pre-integrated with CAST or third-party Ethernet MAC cores.

CAST believes the TCPIP-100G is among the industry's most capable standalone TCP/IP hardware stack IP offerings for both ASIC and FPGA implementation.