Search for Verification IP

HBM2E Memory Model

• Supports HBM2E memory devices from all leading vendors.
• Supports 100% of HBM2E protocol standard specification.

OpenCAPI Verification IP

• Compliant with OpenCAPI Specification versions 3.0 and 3.1
• Complete OpenCAPI Tx/Rx functionality.
• Supports the Data Link Layer and Transaction Layer of OpenCAPI Specification.

AMBA AXI5 Verification IP

• Compliant to the latest ARMâ„¢ AMBA AXI5 & AXI5 lite.
• Compatible to AXI3, AXI4 Protocol Specification v2.0 referred to as AXI4, AXI4-Lite and AXI4 Stream.

JESD204C Verification IP

• Compliant to the latest JESD204C specification by JEDEC
• Backward compatible to all the previous versions of JESD204

PCIe Gen 5 Verification IP

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog

Synthesizable MIPI I3C Bus Functional Model

• Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
• Fully synthesizable SystemVerilog/Verilog RTL

Synthesizable LPDDR3 Bus Functional Model

Synthesizable DDR3 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

Synthesizable DDR4 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

USB 3.2 with xHCI & Retimer Verification IP

• Fully compliant with USB 3.2 specification, xHCI 1.1 and PIPE v4.4.1
• Specification with backward compatibility to USB 2.0 .

Synthesizable LPDDR4 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model
• Fully synthesizable SystemVerilog/Verilog RTL

I3C 1.0 + I2C 4.0 + SMBus 2.0 Verification IP

• Master and Slave models can be used in active and monitor supporting transmit and receive modes and multiple bus speeds (Sm, Fm, Fm+, Hs, Umm)

HBM2E Memory Model

• Supports HBM2E memory devices from all leading vendors.
• Supports 100% of HBM2E protocol standard specification.

AMBA AXI4 Verification IP

Source Code Test Suites AXI Interconnect

Gigabit Ethernet Verification Component

AXI4-Lite UVM/OVM SV based Master Verification IP

FlexRay Verification IP

• Supports Node and Star BFMs
• Node-level and global parameter class support
• Single and dual channel active star and passive bus topologies

AXI4-Lite UVM/OVM SV based Slave Verification IP

• Supports all transaction burst length 1
• Supports Data bus width 32/64-bit
• Supports write Strobes

AMBA AXI Verification IP (VIP)

VC Verification IP for AMBA 4 AXI

APB UVM/OVM 4.0/3.0 SV Slave Verification IP

USB 3.0 OVM/UVM Host Verification IP

Gigabit Ethernet MAC SystemVerilog OVM VIP