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New Verification IP
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JESD204C Verification IP
- Compliant to the latest JESD204C specification by JEDEC
- Backward compatible to all the previous versions of JESD204
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PCIe Gen 5 Verification IP
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
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Synthesizable MIPI I3C Bus Functional Model
- Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
- Fully synthesizable SystemVerilog/Verilog RTL
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Synthesizable LPDDR3 Bus Functional Model
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Synthesizable DDR3 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
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Synthesizable DDR4 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
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USB 3.2 with xHCI & Retimer Verification IP
- Fully compliant with USB 3.2 specification, xHCI 1.1 and PIPE v4.4.1
- Specification with backward compatibility to USB 2.0 .
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Synthesizable LPDDR4 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
- Fully synthesizable SystemVerilog/Verilog RTL
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I3C 1.0 + I2C 4.0 + SMBus 2.0 Verification IP
- Master and Slave models can be used in active and monitor supporting transmit and receive modes and multiple bus speeds (Sm, Fm, Fm+, Hs, Umm)
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CCIX Verifiction IP
- CCIX home agent model incorporating configurable number of request and slave agents, interconnect, and directory agents
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MIPI I3C Verification IP
- //www.design-reuse.com/vip/admin/products.php?mode=edit&id=1116
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Ethernet 400G/200G Verification IP
- Provides Ethernet 200G according to IEEE draft P802.3bs
- Provides Ethernet 400G according to IEEE Draft P802.3bs
Top Verification IP
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1
AMBA AHB and APB Bus Monitor
- Compliant with the AMBA 2.0 specification
- Supports AMBA AHB and AMBA APB
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2
AMBA AXI4 Verification IP
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VC Verification IP for AMBA 4 AXI
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AXI VIP (AXI4 + AXI4 Stream + ACE + AXI3)
- Comprehensive support for AMBA AXI3, AXI4, AXI4-Lite, AXI4 Stream, and ACE including BFMs for master, slave, and N-port interconnect
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JESD204C Verification IP
- Compliant to the latest JESD204C specification by JEDEC
- Backward compatible to all the previous versions of JESD204
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Fully configurable Master, Slave or Monitor IP for verifying any AXI-based interface
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Source Code Test Suites PCIe
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Synthesizable LPDDR4 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
- Fully synthesizable SystemVerilog/Verilog RTL
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Source Code Test Suites AXI Interconnect
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Synthesizable MIPI I3C Bus Functional Model
- Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
- Fully synthesizable SystemVerilog/Verilog RTL
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VC Verification IP for Ethernet
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I3C 1.0 + I2C 4.0 + SMBus 2.0 Verification IP
- Master and Slave models can be used in active and monitor supporting transmit and receive modes and multiple bus speeds (Sm, Fm, Fm+, Hs, Umm)
¹ Top Verification IP Over the Last Two Weeks (Last update: Apr. 15)
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