Search for Verification IP

MPEG-2 TS Verification IP

• Full MPEG-2 TS Transmitter and Receiver functionality.
• Supports the combination of the video and audio coding methods defined in Parts 2 and 3 of ISO/IEC 13818

TileLink Verification IP (VIP)

• Plugs into existing verification environments
• Rapid test bench integration reduces time to first test

MIPI SPMI Verification IP (VIP)

• SystemVerilog coverage infrastructure for extendable coverage
• Callback-based error injection capability for creation of illegal stimulus from the VIP

Ethernet 100GPL (802.3ck) Verification IP (VIP)

• SV coverage infrastructure for extendable coverage
• Callback-based error injection capability for creation of illegal stimulus from the VIP

CXL Verification IP

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure highest levels of quality

Display Port 2.0 Verification IP

• Full Display port 2.0 source device and sink device functionality.
• Supports backward compatibility with previous versions upto DPv1.4a

Flash Octal SPI (OSPI) Verification IP

• Supports Extended SPI mode as well as Octal SDR and DDR mode (Single I/O and Octal I/O)

DisplayPort 2.0 Verification IP (VIP)

• Plugs into existing verification environments
• Rapid testbench integration reduces time to first test
• Incorporates expertise acquired through many prior applications

TPM Verification IP

• Full TPM master device and slave device functionality.
• Compliant to the Trusted Computing Group (TCG) Trusted Platform Module(TPM) Version 1.1b/1.2 and 2.0 Specification

GDDR6 UVM Verification IP

• Fully compliance with JEDEC Specification JESD250A.
• Support DQ data rate up to 12 Gbps per pin.
• Support Low powe mode features.

USB4 Verification IP (VIP)

• Support verification of all protocol layers and configurations
• Callback-based error injection capability for creation of illegal stimulus from the VIP.

VC Verification IP for CPRI

• CPRI specification 7.0
• Single agent, can be configured as RE or REC
• Multiple ports, with master or slave characteristics

AMBA 3 APB Verification IP with compliance testsuite

UART UVM Verification IP

AHB-Lite 3.0 UVM/OVM SV Master Verification IP

MIPI DSI UVM Verification IP

APB UVM/OVM 4.0/3.0 SV Slave Verification IP

PCIe End Point UVM Verification IP

• Independently controlled egress, ingress traffic, and support for all types of packets.
• PCIe and legacy interrupt support.

Synopsys Verification IP for DDR4 (UDIMM, RDIMM, LDIMM)

MIL-STD-1553 Verification IP with testsuite

AHB-Lite 3.0 UVM/OVM SV Slave Verification IP

DDR SDRAM Model

Gigabit Ethernet Verification Component

Source Code Test Suites MIPI CSI-2