Search for Verification IP

OpenCAPI Verification IP

• Compliant with OpenCAPI Specification versions 3.0 and 3.1
• Complete OpenCAPI Tx/Rx functionality.
• Supports the Data Link Layer and Transaction Layer of OpenCAPI Specification.

AMBA AXI5 Verification IP

• Compliant to the latest ARMâ„¢ AMBA AXI5 & AXI5 lite.
• Compatible to AXI3, AXI4 Protocol Specification v2.0 referred to as AXI4, AXI4-Lite and AXI4 Stream.

JESD204C Verification IP

• Compliant to the latest JESD204C specification by JEDEC
• Backward compatible to all the previous versions of JESD204

PCIe Gen 5 Verification IP

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog

Synthesizable MIPI I3C Bus Functional Model

• Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
• Fully synthesizable SystemVerilog/Verilog RTL

Synthesizable LPDDR3 Bus Functional Model

Synthesizable DDR3 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

Synthesizable DDR4 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

USB 3.2 with xHCI & Retimer Verification IP

• Fully compliant with USB 3.2 specification, xHCI 1.1 and PIPE v4.4.1
• Specification with backward compatibility to USB 2.0 .

Synthesizable LPDDR4 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model
• Fully synthesizable SystemVerilog/Verilog RTL

I3C 1.0 + I2C 4.0 + SMBus 2.0 Verification IP

• Master and Slave models can be used in active and monitor supporting transmit and receive modes and multiple bus speeds (Sm, Fm, Fm+, Hs, Umm)

CCIX Verifiction IP

• CCIX home agent model incorporating configurable number of request and slave agents, interconnect, and directory agents

OpenCAPI Verification IP

• Compliant with OpenCAPI Specification versions 3.0 and 3.1
• Complete OpenCAPI Tx/Rx functionality.
• Supports the Data Link Layer and Transaction Layer of OpenCAPI Specification.

Complete Verification IP Portfolio

AHB-Lite 3.0 UVM/OVM SV Slave Verification IP

AHB-Lite 3.0 UVM/OVM SV Master Verification IP

UART UVM Verification IP

SPI Master/Slave Verification IP

• Supports both Master and Slave
• Supports Bidirectional Mode
• Programmable clock polarity

MIPI I3C Verification IP

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Serial Peripheral Interface Verification IP

JESD204C Verification IP

• Compliant to the latest JESD204C specification by JEDEC
• Backward compatible to all the previous versions of JESD204

JESD204B Verification IP with compliance testsuite

MIPI CSI-2 with C phy Verification IP

• Compliant to MIPI CSI-2 Interface Specification version 1.1 and MIPI D-PHY version 1.1

AMBA 3 AHB Verification IP with compliance testsuite

• Compliant with ARM AMBA 3 AHB specification.
• Supports ARM11 extension
• Supports both AHB and AHB lite operation.