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MIPI D-PHY Transmitter - Designed for TSMC 40nmLP for Automotive
New Verification IP
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MIPI SPMI Verification IP (VIP)
- SystemVerilog coverage infrastructure for extendable coverage
- Callback-based error injection capability for creation of illegal stimulus from the VIP
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Ethernet 100GPL (802.3ck) Verification IP (VIP)
- SV coverage infrastructure for extendable coverage
- Callback-based error injection capability for creation of illegal stimulus from the VIP
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CXL Verification IP
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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Display Port 2.0 Verification IP
- Full Display port 2.0 source device and sink device functionality.
- Supports backward compatibility with previous versions upto DPv1.4a
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Flash Octal SPI (OSPI) Verification IP
- Supports Extended SPI mode as well as Octal SDR and DDR mode (Single I/O and Octal I/O)
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DisplayPort 2.0 Verification IP (VIP)
- Plugs into existing verification environments
- Rapid testbench integration reduces time to first test
- Incorporates expertise acquired through many prior applications
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TPM Verification IP
- Full TPM master device and slave device functionality.
- Compliant to the Trusted Computing Group (TCG) Trusted Platform Module(TPM) Version 1.1b/1.2 and 2.0 Specification
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GDDR6 UVM Verification IP
- Fully compliance with JEDEC Specification JESD250A.
- Support DQ data rate up to 12 Gbps per pin.
- Support Low powe mode features.
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USB4 Verification IP (VIP)
- Support verification of all protocol layers and configurations
- Callback-based error injection capability for creation of illegal stimulus from the VIP.
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VC Verification IP for CPRI
- CPRI specification 7.0
- Single agent, can be configured as RE or REC
- Multiple ports, with master or slave characteristics
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GDDR7 Memory Model
- Supports GDDR7 memory devices from all leading vendors.
- Supports 100% of GDDR7 protocol draft JEDEC specification.
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TileLink Verification IP
- Supports TileLink Master, TileLink Slave, TileLink Interconnect, TileLink Monitor and TileLink Checker.
Top Verification IP
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1
PCIe End Point UVM Verification IP
- Independently controlled egress, ingress traffic, and support for all types of packets.
- PCIe and legacy interrupt support.
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2
Ethernet 100GPL (802.3ck) Verification IP (VIP)
- SV coverage infrastructure for extendable coverage
- Callback-based error injection capability for creation of illegal stimulus from the VIP
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3
VC Verification IP for AMBA 4 AXI
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MIPI SPMI Verification IP (VIP)
- SystemVerilog coverage infrastructure for extendable coverage
- Callback-based error injection capability for creation of illegal stimulus from the VIP
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5
AMBA AXI4 Verification IP
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AXI4-Lite UVM/OVM SV based Slave Verification IP
- Supports all transaction burst length 1
- Supports Data bus width 32/64-bit
- Supports write Strobes
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MIPI DSI-2 Verification IP
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8
MII/SMII/RMII/GMII/RGMII Verification IP
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9
PCI Express 4.0/3.1 VIP (PCIe)
- Comprehensive support for PCI Express standard for 1.1, 2.1, 3.0, SR-IOV, SOP/PQI, and Intel PIPE PHY including BFMs for N-port Root Complex, Endpoint, SR-IOV Endpoint, N-port Switch, and PIPE-compliant PH
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10
VC Verification IP for Ethernet
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11
Interlaken Verification IP with compliance testsuite
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12
VESA DSC Video Encoder and Decoder Verification IP
- Supports all mandatory and optional VESA DSC v1.1 features
- Based on the latest VESA C-model version 1.31
¹ Top Verification IP Over the Last Two Weeks (Last update: Nov. 17)
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