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New Verification IP
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MIPI I3C Verification IP with IBI feature enabled
- Push-pull mode,
- Open drain switching,
- CCC, command
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UCIe Verification IP
- Support latest PCIe Gen5/6 and CXL 2.0/3.0
- Device and Retimer supported
- Multiple stacks / multiple protocol
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Synthesizable DDR5 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
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SGPIO Verification IP
- Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7.
- Full SGPIO Initiator and SGPIO Target functionality.
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Ethernet TSN Verification IP (VIP)
- Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
- Predefined protocol checkers to evaluate the compliance of the DUT model to protocol requirements
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MIPI TWP Verification IP
- Compliant with MIPI TWP Specification version 1.1.
- Supports ATB interface.
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CXL 3.0 Verification IP
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure the highest levels of quality.
- 24X5 customer support.
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Simulation VIP for Ethernet 5G Network
- SyncE
- eCPRI
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CXS a/b Verification IP
- Compliant with the CXS Version A specification
- Verification IP configurable as CXS ON-CHIP and OFF_CHIP Interconnect
- Support for different CXS Resets
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RISC-V formal Verification IP
- Push-button, GUI based
- Efficient bug hunting
- Predictable run times for proving instruction-set-architecture
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MIPI A-PHY Verification IP
- Compliant to MIPI A-PHY Specification Version 1.1 with APPI interface.
- Support all C-Port, D-Port, and Q-Port.
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AMBA DTI Verification IP (VIP)
- Bypass Translation Mode Support
- Connect and Disconnect Message Group
- DTI-TBU Caching Module
Top Verification IP
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1
UCIe Verification IP
- Support latest PCIe Gen5/6 and CXL 2.0/3.0
- Device and Retimer supported
- Multiple stacks / multiple protocol
-
2
Synthesizable DDR5 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
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3
VC Verification IP for I2C
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4
MIPI RFFE 3.0 Verification IP (VIP)
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5
eCPRI Verification IP
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6
AHB + APB VIP
- Comprehensive support for AMBA AHB
- Complex traffic sequence generators for normal and error scenarios
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7
MIPI SPMI Verification IP (VIP)
- SystemVerilog coverage infrastructure for extendable coverage
- Callback-based error injection capability for creation of illegal stimulus from the VIP
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8
DDR4 Memory VIP
- DDR models support JEDEC Low Power Memory Device and DDR4 DRAM (JESD79-4)
- Flexible and unencypted SystemVerilog timing class models all timing parameters
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9
I2C Verification IP
¹ Top Verification IP Over the Last Two Weeks (Last update: Nov. 27)
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