Search for Verification IP

JESD204 Verification IP

• High Performance
• Richly Featured
• Easy to use

ARINC 664 Verification IP

• Supports IEEE 802.3 10/100 Mbit/s Full duplex Ethernet links
• Supports all word structures and protocol necessary to establish bus communication as per the specs.

PCIe Gen 6 Verification IP

• Compliant with PCI Express Specifications 6.0 v0.7(64GT/s), 5.0 v1.0(32GT/s), 4.0 v1.0 (16GT/s), 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).

Ethernet 10BASE-T1S Verification IP

• Faster testbench development and more complete verification of 10BASE-T1S designs.

Synthesizable LPDDR5 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

Ethernet Verification IP (10/100M, 1 / 10 / 25 / 40 / 50 / 100 / 200 / 400 / 800G)

• Comprehensive support for IEEE 802.1 and 802.3 standards
• Multi-port MAC, PHY, Bridge models

JTAG DTM Verification IP

• Compliant to RISC-V Debug Specification 0.13.2, JTAG DTM provided by SiFive, Inc.

FPU Verification IP

• Compliant to RISC-V Specification and IEEE 754 floating point standard.
• Configurable bits (half, single, double and quad precision).

RI5CY Verification IP

• Compliant to RI5CY specification for PULPmicroprocessor cores provided be Integrated Systems Lab, Inc.

Platform Level Interrupt Controller Verification IP

• Compliant to RISC-V Privilege Spec,provided by SiFive, Inc.
• Supports all types of interrupt controller configurations

PIPE5.1 VIP using UVM based methodology with 100% coverage

• VIP for MAC layer/ SerDes.
• Plug and play feature
• Support 32GT/s.

MIPI APHY Verification IP

• Compliant with MIPI A-PHY 1.0 specification.
• Support single lane, point-to-point and serial communication technology.

AMBA AHB Verification IP

Source Code Test Suites AXI Interconnect

Verification IP AXI4

I2C Master and Slave OVM/UVM Verification IP

• Highly Flexible, Independent and Configurable I2C Master VIP
• Proven against Silicon Proven VIP

Gigabit Ethernet MAC SystemVerilog OVM VIP

AHB + APB VIP

• Comprehensive support for AMBA AHB
• Complex traffic sequence generators for normal and error scenarios

APB UVM/OVM 4.0/3.0 SV Slave Verification IP

AMBA 2.0 AHB Verification IP

QSPI (Quad Serial Peripheral Interface) Verification IP

DDR4 Memory VIP

• DDR models support JEDEC Low Power Memory Device and DDR4 DRAM (JESD79-4)
• Flexible and unencypted SystemVerilog timing class models all timing parameters

AMBA AXI4 Verification IP

AXI VIP (AXI4 + AXI4 Stream + ACE + AXI3)

• Comprehensive support for AMBA AXI3, AXI4, AXI4-Lite, AXI4 Stream, and ACE including BFMs for master, slave, and N-port interconnect