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New Verification IP
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WDT Verification IP
- The Watchdog Timer (WDT) regains control in case of system failure to increase application reliability.
- The WDT can generate a reset or an interrupt when the counter reaches a given timeout value.
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GPIO Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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Simulation VIP for AMBA LTI
- LTI active and passive VIP supports both the specification version LTI-A and LTI-B
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Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- UVM building blocks
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Universal Chiplet Interconnect Express (UCIe) Verification IP
- Supports Universal Chiplet Interconnect Express Specification Version 1.0, February 2022.
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SPMI Verification IP
- Compliant with MIPI SPMI(1.0 and 2.0) specification.
- Supports multi-master and multi-slave model.
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BoW Verification IP
- Compliant to ODSA Transaction and Link Layer Specification for BoW Interfaces and Bunch of Wires (BoW) PHY specification
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USB4 v2.0 Verification IP
- Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
- Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
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MASS Solution Verification IP
- Support full functionality of APHY as a physical layer
- Support Different PAL for multiple adaption layers for A-pkt conversion
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UCIe Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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TCP/TCPSW Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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Simulation VIP for MIPI SoundWire-I3S
- Support testbench language interfaces for SystemVerilog and UVM
- Generates constrained-random bus traffic with predefined error injection
Top Verification IP
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AMBA AXI4 Verification IP
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Synthesizable MIPI I3C Bus Functional Model
- Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
- Fully synthesizable SystemVerilog/Verilog RTL
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3
VC Verification IP for MIPI CSI-2 (C-PHY / D-PHY)
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10
MIPI APHY Verification IP
- Compliant with MIPI A-PHY 1.0 specification.
- Support single lane, point-to-point and serial communication technology.
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11
Ethernet GMII TBI (8b/10b) Verification IP
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Open LVDS Display Interface (OpenLDI) Verification IP
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