Search for Verification IP

TCP/TCPSW Verification IP

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality

Simulation VIP for MIPI SoundWire-I3S

• Support testbench language interfaces for SystemVerilog and UVM
• Generates constrained-random bus traffic with predefined error injection

Ethernet Preemption Verification IP

• Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)

MIPI A-PHY Verification IP

• Supports MIPI A-PHY specification 1.0 and 1.1
• Supports single lane and dual lane, point-to-point and serial communication technology

Simulation VIP for UCIE

• Support testbench language interfaces for SystemVerilog, UVM
• Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation

MIPI I3C Verification IP with IBI feature enabled

• Push-pull mode,
• Open drain switching,
• CCC, command

UCIe Verification IP

• Support latest PCIe Gen5/6 and CXL 2.0/3.0
• Device and Retimer supported
• Multiple stacks / multiple protocol

Synthesizable DDR5 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

SGPIO Verification IP

• Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7.
• Full SGPIO Initiator and SGPIO Target functionality.

Simulation VIP for AMBA ATP

• Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
• Predefined protocol checkers to evaluate the compliance of the DUT model to protocol requirements

MIPI TWP Verification IP

• Compliant with MIPI TWP Specification version 1.1.
• Supports ATB interface.

CXL 3.0 Verification IP

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
• Unique development methodology to ensure the highest levels of quality.
• 24X5 customer support.

PCI Express Verification IP

JESD204 Verification IP

• High Performance
• Richly Featured
• Easy to use

VC Verification IP for AMBA 4 AXI

AMBA AXI4 Verification IP

MIPI APHY Verification IP

• Compliant with MIPI A-PHY 1.0 specification.
• Support single lane, point-to-point and serial communication technology.

PCI-X Verification Component

MIPI A-PHY Verification IP

• Supports MIPI A-PHY specification 1.0 and 1.1
• Supports single lane and dual lane, point-to-point and serial communication technology

MIPI I3C Verification IP

• //www.design-reuse.com/vip/admin/products.php?mode=edit&id=1116

MIPI I3C Verification IP with IBI feature enabled

• Push-pull mode,
• Open drain switching,
• CCC, command

I3C 1.0 + I2C 4.0 + SMBus 2.0 Verification IP

• Master and Slave models can be used in active and monitor supporting transmit and receive modes and multiple bus speeds (Sm, Fm, Fm+, Hs, Umm)

PCIe Gen 5 Verification IP

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog

Simulation VIP for MIPI CSI-2

• Industry's first CSI-2 VIP
• Part of the broadest line of MIPI simulation VIP
• Features optional Accelerated VIP