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New Verification IP
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WDT Verification IP
- The Watchdog Timer (WDT) regains control in case of system failure to increase application reliability.
- The WDT can generate a reset or an interrupt when the counter reaches a given timeout value.
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GPIO Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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Simulation VIP for AMBA LTI
- LTI active and passive VIP supports both the specification version LTI-A and LTI-B
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Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- UVM building blocks
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Universal Chiplet Interconnect Express (UCIe) Verification IP
- Supports Universal Chiplet Interconnect Express Specification Version 1.0, February 2022.
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SPMI Verification IP
- Compliant with MIPI SPMI(1.0 and 2.0) specification.
- Supports multi-master and multi-slave model.
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BoW Verification IP
- Compliant to ODSA Transaction and Link Layer Specification for BoW Interfaces and Bunch of Wires (BoW) PHY specification
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USB4 v2.0 Verification IP
- Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
- Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
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MASS Solution Verification IP
- Support full functionality of APHY as a physical layer
- Support Different PAL for multiple adaption layers for A-pkt conversion
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UCIe Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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TCP/TCPSW Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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Simulation VIP for MIPI SoundWire-I3S
- Support testbench language interfaces for SystemVerilog and UVM
- Generates constrained-random bus traffic with predefined error injection
Top Verification IP
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1
WDT Verification IP
- The Watchdog Timer (WDT) regains control in case of system failure to increase application reliability.
- The WDT can generate a reset or an interrupt when the counter reaches a given timeout value.
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2
Synthesizable MIPI I3C Bus Functional Model
- Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
- Fully synthesizable SystemVerilog/Verilog RTL
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3
GPIO Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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4
Simulation VIP for MIPI I3C
- The I3C VIP complies with MIPI I3C specification version 0.7 which is still under review by the MIPI Alliance Organization.
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5
MIPI I3C Verification IP
- //www.design-reuse.com/vip/admin/products.php?mode=edit&id=1116
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6
DDR5 DFI Verification IP
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10
MIPI CSI-2 with C phy Verification IP
- Compliant to MIPI CSI-2 Interface Specification version 1.1 and MIPI D-PHY version 1.1
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11
Fully configurable Master, Slave or Monitor IP for verifying any AXI-based interface
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12
AMBA 5 AHB Bus Verification IP
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