Search for Verification IP

WDT Verification IP

• The Watchdog Timer (WDT) regains control in case of system failure to increase application reliability.
• The WDT can generate a reset or an interrupt when the counter reaches a given timeout value.

GPIO Verification IP

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality

Simulation VIP for AMBA LTI

• LTI active and passive VIP supports both the specification version LTI-A and LTI-B

Simulation VIP for UCIE

• Support testbench language interfaces for SystemVerilog, UVM
• UVM building blocks

Universal Chiplet Interconnect Express (UCIe) Verification IP

• Supports Universal Chiplet Interconnect Express Specification Version 1.0, February 2022.

SPMI Verification IP

• Compliant with MIPI SPMI(1.0 and 2.0) specification.
• Supports multi-master and multi-slave model.

BoW Verification IP

• Compliant to ODSA Transaction and Link Layer Specification for BoW Interfaces and Bunch of Wires (BoW) PHY specification

USB4 v2.0 Verification IP

• Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
• Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.

MASS Solution Verification IP

• Support full functionality of APHY as a physical layer
• Support Different PAL for multiple adaption layers for A-pkt conversion

UCIe Verification IP

• Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
• Unique development methodology to ensure highest levels of quality

TCP/TCPSW Verification IP

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality

Simulation VIP for MIPI SoundWire-I3S

• Support testbench language interfaces for SystemVerilog and UVM
• Generates constrained-random bus traffic with predefined error injection

AMBA AXI4 Verification IP

Synthesizable MIPI I3C Bus Functional Model

• Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
• Fully synthesizable SystemVerilog/Verilog RTL

VC Verification IP for MIPI CSI-2 (C-PHY / D-PHY)

DDR + LPDDR Memory Controller VIP

SRAM Verification IP

LPDDR DFI Verification IP

LPDDR Memory Model

Ethernet 1G Verification IP

JTAG (IEEE 1149.1/1149.6) Verification IP

MIPI APHY Verification IP

• Compliant with MIPI A-PHY 1.0 specification.
• Support single lane, point-to-point and serial communication technology.

Ethernet GMII TBI (8b/10b) Verification IP

Open LVDS Display Interface (OpenLDI) Verification IP