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New Verification IP
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GDDR6 UVM Verification IP
- Fully compliance with JEDEC Specification JESD250A.
- Support DQ data rate up to 12 Gbps per pin.
- Support Low powe mode features.
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USB4 Verification IP (VIP)
- Support verification of all protocol layers and configurations
- Callback-based error injection capability for creation of illegal stimulus from the VIP.
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VC Verification IP for CPRI
- CPRI specification 7.0
- Single agent, can be configured as RE or REC
- Multiple ports, with master or slave characteristics
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GDDR7 Memory Model
- Supports GDDR7 memory devices from all leading vendors.
- Supports 100% of GDDR7 protocol draft JEDEC specification.
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TileLink Verification IP
- Supports TileLink Master, TileLink Slave, TileLink Interconnect, TileLink Monitor and TileLink Checker.
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Ethernet-TSN Verification IP
- Faster testbench development and more complete verification of Ethernet-TSN designs
- Easy to use command interface simplifies testbench control and configuration of TX and RX
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Gen Z Verification IP
- Multiple Physical Layers supported which can be selected as per medium
- Capable of Power Management and support for all low power states
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SD Card Verification IP
- Compatible with all the versions V1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 6.10, 7.00
- Supports all Capacity of Memory i.e.
- Standard Capacity SD Memory Card (SDSC)
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SD Express Card Verification IP
- Compliant to SD Specification v7.00
- SD Express card supports NVMe protocol over PCIe Interface
- Supports SD and PCIe Mode
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TS5 Verification IP
- Implemented in native OpenVera, Verilog, SystemC and SystemVerilog.
- Supported RVM, AVM, VMM, OVM, UVM and non-standard verify env.
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HBM2E Memory Model
- Supports HBM2E memory devices from all leading vendors.
- Supports 100% of HBM2E protocol standard specification.
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OpenCAPI Verification IP
- Compliant with OpenCAPI Specification versions 3.0 and 3.1
- Complete OpenCAPI Tx/Rx functionality.
- Supports the Data Link Layer and Transaction Layer of OpenCAPI Specification.
Top Verification IP
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1
GDDR6 UVM Verification IP
- Fully compliance with JEDEC Specification JESD250A.
- Support DQ data rate up to 12 Gbps per pin.
- Support Low powe mode features.
-
2
USB4 Verification IP (VIP)
- Support verification of all protocol layers and configurations
- Callback-based error injection capability for creation of illegal stimulus from the VIP.
-
3
VC Verification IP for CPRI
- CPRI specification 7.0
- Single agent, can be configured as RE or REC
- Multiple ports, with master or slave characteristics
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10
Source Code Test Suites PCIe
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11
Ethernet-TSN Verification IP
- Faster testbench development and more complete verification of Ethernet-TSN designs
- Easy to use command interface simplifies testbench control and configuration of TX and RX
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12
AMBA AXI4 Verification IP
¹ Top Verification IP Over the Last Two Weeks (Last update: Apr. 21)
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