Search for Verification IP

Ethernet 10BASE-T1S Verification IP

• Faster testbench development and more complete verification of 10BASE-T1S designs.

Synthesizable LPDDR5 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

Ethernet Verification IP (10/100M, 1 / 10 / 25 / 40 / 50 / 100 / 200 / 400 / 800G)

• Comprehensive support for IEEE 802.1 and 802.3 standards
• Multi-port MAC, PHY, Bridge models

JTAG DTM Verification IP

• Compliant to RISC-V Debug Specification 0.13.2, JTAG DTM provided by SiFive, Inc.

FPU Verification IP

• Compliant to RISC-V Specification and IEEE 754 floating point standard.
• Configurable bits (half, single, double and quad precision).

RI5CY Verification IP

• Compliant to RI5CY specification for PULPmicroprocessor cores provided be Integrated Systems Lab, Inc.

Platform Level Interrupt Controller Verification IP

• Compliant to RISC-V Privilege Spec,provided by SiFive, Inc.
• Supports all types of interrupt controller configurations

PIPE5.1 VIP using UVM based methodology with 100% coverage

• VIP for MAC layer/ SerDes.
• Plug and play feature
• Support 32GT/s.

MIPI APHY Verification IP

• Compliant with MIPI A-PHY 1.0 specification.
• Support single lane, point-to-point and serial communication technology.

AMBA AXI5 Verification IP using UVM based methodology with 100% coverage

• Reduced time to verify your DUT
• Very easy to integrate
• Accelerate your time to market

Spacewire Verification IP

• Available in UVM, System Verilog.
• Compliant to Specification ECSS-E-ST-50-12 C rev 1.
• Supports speeds between 2Mb/s to 400Mb/s

CPRI verification IP

• Compatible with CPRI version v7.0 as well as previous versions.
• Transmitter/Receiver function
• Supports line bit rates of CPRI specification

Ethernet 10BASE-T1S Verification IP

• Faster testbench development and more complete verification of 10BASE-T1S designs.

AHB + APB VIP

• Comprehensive support for AMBA AHB
• Complex traffic sequence generators for normal and error scenarios

Gigabit Ethernet MAC SystemVerilog OVC Verification IP

Gigabit Ethernet MAC SystemVerilog OVM VIP

VC Verification IP for PCIe

Ethernet - up to 400G Verification IP

MIPI C-PHY UVM Verification IP

• Compliance: MIPI 1.0 Specification
• Language: System Verilog
• Methodology: UVM 1.1

VC Verification IP for Ethernet

UART UVM Verification IP

I2C Master and Slave OVM/UVM Verification IP

• Highly Flexible, Independent and Configurable I2C Master VIP
• Proven against Silicon Proven VIP

AMBA AXI 4.0 Verification IP

SRAM Verification IP