Search for Verification IP

JESD204 Verification IP

• High Performance
• Richly Featured
• Easy to use

ARINC 664 Verification IP

• Supports IEEE 802.3 10/100 Mbit/s Full duplex Ethernet links
• Supports all word structures and protocol necessary to establish bus communication as per the specs.

PCIe Gen 6 Verification IP

• Compliant with PCI Express Specifications 6.0 v0.7(64GT/s), 5.0 v1.0(32GT/s), 4.0 v1.0 (16GT/s), 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).

Ethernet 10BASE-T1S Verification IP

• Faster testbench development and more complete verification of 10BASE-T1S designs.

Synthesizable LPDDR5 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

Ethernet Verification IP (10/100M, 1 / 10 / 25 / 40 / 50 / 100 / 200 / 400 / 800G)

• Comprehensive support for IEEE 802.1 and 802.3 standards
• Multi-port MAC, PHY, Bridge models

JTAG DTM Verification IP

• Compliant to RISC-V Debug Specification 0.13.2, JTAG DTM provided by SiFive, Inc.

FPU Verification IP

• Compliant to RISC-V Specification and IEEE 754 floating point standard.
• Configurable bits (half, single, double and quad precision).

RI5CY Verification IP

• Compliant to RI5CY specification for PULPmicroprocessor cores provided be Integrated Systems Lab, Inc.

Platform Level Interrupt Controller Verification IP

• Compliant to RISC-V Privilege Spec,provided by SiFive, Inc.
• Supports all types of interrupt controller configurations

PIPE5.1 VIP using UVM based methodology with 100% coverage

• VIP for MAC layer/ SerDes.
• Plug and play feature
• Support 32GT/s.

MIPI APHY Verification IP

• Compliant with MIPI A-PHY 1.0 specification.
• Support single lane, point-to-point and serial communication technology.

AXI 4.0/3.0 UVM/OVM SV Slave Verification IP

AHB-Lite 3.0 UVM/OVM SV Master Verification IP

LPDDR4 Memory Model

AMBA AXI3 Verification IP

I2C Master and Slave OVM/UVM Verification IP

• Highly Flexible, Independent and Configurable I2C Master VIP
• Proven against Silicon Proven VIP

Verification IP for DDR3 (UDIMM, RDIMM, LDIMM)

QSPI (Quad Serial Peripheral Interface) Verification IP

JTAG DTM Verification IP

• Compliant to RISC-V Debug Specification 0.13.2, JTAG DTM provided by SiFive, Inc.

AMBA AXI5 Interconnect Verification IP

SPI (Serial Peripheral Interface) Flash Verification IP

Synopsys Verification IP for LPDDR4

• August 2014 JEDEC LPDDR4 Standard
• 4Gb to 32Gb densities and x16 SRAM devices

IEEE 1149.7 Compact JTAG (cJTAG) uVC