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New Verification IP
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MPEG-2 TS Verification IP
- Full MPEG-2 TS Transmitter and Receiver functionality.
- Supports the combination of the video and audio coding methods defined in Parts 2 and 3 of ISO/IEC 13818
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TileLink Verification IP (VIP)
- Plugs into existing verification environments
- Rapid test bench integration reduces time to first test
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MIPI SPMI Verification IP (VIP)
- SystemVerilog coverage infrastructure for extendable coverage
- Callback-based error injection capability for creation of illegal stimulus from the VIP
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Ethernet 100GPL (802.3ck) Verification IP (VIP)
- SV coverage infrastructure for extendable coverage
- Callback-based error injection capability for creation of illegal stimulus from the VIP
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CXL Verification IP
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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Display Port 2.0 Verification IP
- Full Display port 2.0 source device and sink device functionality.
- Supports backward compatibility with previous versions upto DPv1.4a
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Flash Octal SPI (OSPI) Verification IP
- Supports Extended SPI mode as well as Octal SDR and DDR mode (Single I/O and Octal I/O)
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DisplayPort 2.0 Verification IP (VIP)
- Plugs into existing verification environments
- Rapid testbench integration reduces time to first test
- Incorporates expertise acquired through many prior applications
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TPM Verification IP
- Full TPM master device and slave device functionality.
- Compliant to the Trusted Computing Group (TCG) Trusted Platform Module(TPM) Version 1.1b/1.2 and 2.0 Specification
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GDDR6 UVM Verification IP
- Fully compliance with JEDEC Specification JESD250A.
- Support DQ data rate up to 12 Gbps per pin.
- Support Low powe mode features.
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USB4 Verification IP (VIP)
- Support verification of all protocol layers and configurations
- Callback-based error injection capability for creation of illegal stimulus from the VIP.
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VC Verification IP for CPRI
- CPRI specification 7.0
- Single agent, can be configured as RE or REC
- Multiple ports, with master or slave characteristics
Top Verification IP
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1
PCIe End Point UVM Verification IP
- Independently controlled egress, ingress traffic, and support for all types of packets.
- PCIe and legacy interrupt support.
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2
UART UVM Verification IP
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3
Ethernet 10/100/1G/10G Verification IP (VIP)
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7
MIPI CSI2 With D-PHY Verification IP
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8
DDR4 Memory VIP
- DDR models support JEDEC Low Power Memory Device and DDR4 DRAM (JESD79-4)
- Flexible and unencypted SystemVerilog timing class models all timing parameters
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CPRI Verification IP
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10
CXL Verification IP
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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11
USB 2.0 Verification IP with compliance testsuite
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12
VC Verification IP for Ethernet
¹ Top Verification IP Over the Last Two Weeks (Last update: Feb. 16)
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