Search for Verification IP

HBM2E Memory Model

• Supports HBM2E memory devices from all leading vendors.
• Supports 100% of HBM2E protocol standard specification.

OpenCAPI Verification IP

• Compliant with OpenCAPI Specification versions 3.0 and 3.1
• Complete OpenCAPI Tx/Rx functionality.
• Supports the Data Link Layer and Transaction Layer of OpenCAPI Specification.

AMBA AXI5 Verification IP

• Compliant to the latest ARMâ„¢ AMBA AXI5 & AXI5 lite.
• Compatible to AXI3, AXI4 Protocol Specification v2.0 referred to as AXI4, AXI4-Lite and AXI4 Stream.

JESD204C Verification IP

• Compliant to the latest JESD204C specification by JEDEC
• Backward compatible to all the previous versions of JESD204

PCIe Gen 5 Verification IP

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog

Synthesizable MIPI I3C Bus Functional Model

• Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
• Fully synthesizable SystemVerilog/Verilog RTL

Synthesizable LPDDR3 Bus Functional Model

Synthesizable DDR3 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

Synthesizable DDR4 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model

USB 3.2 with xHCI & Retimer Verification IP

• Fully compliant with USB 3.2 specification, xHCI 1.1 and PIPE v4.4.1
• Specification with backward compatibility to USB 2.0 .

Synthesizable LPDDR4 Bus Functional Model

• Fully JEDEC spec functionality compliant and reports any non-compliance issues
• Fully cycle accurate model
• Fully synthesizable SystemVerilog/Verilog RTL

I3C 1.0 + I2C 4.0 + SMBus 2.0 Verification IP

• Master and Slave models can be used in active and monitor supporting transmit and receive modes and multiple bus speeds (Sm, Fm, Fm+, Hs, Umm)

UART UVM Verification IP

AMBA 3 APB Verification IP with compliance testsuite

AMBA AHB Verification IP (VIP)

• AMBA Specification v2.0, AMBA 3 AHB-Lite Protocol specification v1.0, AMBA 5 AHB5 specification update, and ARMv6 AMBA Extensions

JESD204C Verification IP

• Compliant to the latest JESD204C specification by JEDEC
• Backward compatible to all the previous versions of JESD204

PCI Express BFM for FPGA designers

PCI Express Virtual Reality Verification IP

PCI Express 4.0/3.1 VIP (PCIe)

• Comprehensive support for PCI Express standard for 1.1, 2.1, 3.0, SR-IOV, SOP/PQI, and Intel PIPE PHY including BFMs for N-port Root Complex, Endpoint, SR-IOV Endpoint, N-port Switch, and PIPE-compliant PH

PCIe End Point UVM Verification IP

• Independently controlled egress, ingress traffic, and support for all types of packets.
• PCIe and legacy interrupt support.

PCIe Root Complex Verification IP

• Independently controlled egress, ingress traffic, and support for all types of packets.
• Configurable Enumeration sequence support.

Synthesizable MIPI I3C Bus Functional Model

• Fully MIPI I3C specification functionality compliant reporting any non-compliance issues
• Fully synthesizable SystemVerilog/Verilog RTL

AMBA AXI3 Verification IP

SMPTE SDI Verification IP

• Supports 270-Mbps SD-SDI
• Supports 1.5-Gbps HD-SDI
• Supports 3-Gbps SDI