Search News

Design Platform News

• QuickLogic Integrates Synopsys Synplify Synthesis for Best-in-Class Quality of Results (Sunday, February 9, 2025)
• Onsemi's Treo Taps Weebit ReRAM (Sunday, February 9, 2025)
• Axiomise Launches footprint, Area Analyzer for Silicon Design (Wednesday, February 5, 2025)
• Accellera Board Approves Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 Standard for Release (Tuesday, February 4, 2025)
• Cadence Virtuoso Studio advanced optimization enhances MediaTek's efficiency by 30% (Tuesday, February 4, 2025)
• Alchip opens 3DIC ASIC design services (Thursday, January 16, 2025)
• Alchip opens 3DIC ASIC design services (Thursday, January 16, 2025)
• Exostiv Labs Unveils AMD Versal Adaptive SoC Device Support for Exostiv and Exostiv Blade Platforms (Sunday, January 12, 2025)
• Qualitas Semiconductor and Verisilicon signed a licensing agreement for 4nm PCIe 6.0 PHY IP (Wednesday, January 8, 2025)
• Cadence: Leading the EDA Industry with AI-Powered Platforms (Tuesday, January 7, 2025)
• Siemens Xcelerator: Eplan and Siemens Enable Data Interoperability in Machine Engineering (Thursday, January 2, 2025)
• EnSilica PLC Demonstrates Strong Growth and Market Position in ASIC Industry (Friday, December 27, 2024)
• GUC Joins Arm Total Design Ecosystem to Strengthen ASIC Design Services (Monday, December 23, 2024)
• Siemens extends Veloce hardware-assisted verification support of EPGM Ethernet to 1.6 Tbps (Tuesday, December 17, 2024)
• sureCore teams with Sarcina to package cryo chips (Monday, December 16, 2024)
• MosChip selects Cadence tools for the design of HPC Processor "AUM" for C-DAC (Wednesday, December 11, 2024)
• MosChip selects Cadence tools for the design of HPC Processor "AUM" for C-DAC (Tuesday, December 10, 2024)
• Silvaco Joins SMART USA Institute to Propel Digital Twin Innovations Under CHIPS Manufacturing USA Program (Tuesday, December 3, 2024)
• Arteris Deployed by Menta for Edge AI Chiplet Platform (Monday, December 2, 2024)
• Marvell Unveils Industry's First 3nm 1.6 Tbps PAM4 Interconnect Platform to Scale Accelerated Infrastructure (Monday, December 2, 2024)
• HPC customer engages Sondrel for high end chip design (Thursday, November 21, 2024)
• Solid Sands and VyperCore Collaborate to Ensure C/C++ Compliance in New Accelerator Chip Design (Wednesday, November 20, 2024)
• Renesas Introduces Industry's First Complete Memory Interface Chipset Solutions for Second-Generation DDR5 Server MRDIMMs (Tuesday, November 19, 2024)
• NVIDIA Announces Omniverse Real-Time Physics Digital Twins With Industry Software Leaders (Sunday, November 17, 2024)
• Siemens Launches TIA Portal Version 20 Focused on Improved Performance (Friday, November 15, 2024)
• Siemens presents next-generation AI-supported software for electronic system design (Thursday, November 14, 2024)
• Siemens extends Veloce hardware-assisted verification and validation with new Innexis shift-left software (Monday, November 11, 2024)
• Oriole Networks Selects EnSilica as ASIC Partner and Contract Award for Photonics Controller ASIC (Sunday, November 10, 2024)
• Oriole Networks Selects EnSilica as ASIC Partner and Contract Award for Photonics Controller ASIC (Sunday, November 10, 2024)
• Siemens' Tessent In-System Test software enables advanced, deterministic testing throughout the silicon lifecycle (Monday, November 4, 2024)
• Research for the future, application transfer for the present (Sunday, November 3, 2024)
• Faraday Unveils HiSpeedKit?-HS Platform for High-speed Interface IP Verification in SoCs (Tuesday, October 29, 2024)
• Siemens and CELUS collaborate to empower SMBs with AI-powered PCB design (Monday, October 28, 2024)
• Keysight collaborates with Siemens EDA enabling next generation of wireless design (Monday, October 21, 2024)
• EnSilica plc - Award of £2 million Controller ASIC Design Services Contract (Sunday, October 20, 2024)
• Successful tape out of Chip Interfaces' JESD204D IP by a tier 1 semiconductor company (Tuesday, October 15, 2024)
• Agile Analog announces MoU to support new Southern Taiwan IC Design Industry (Monday, October 14, 2024)
• Siemens Updates Simcenter Testlab for Advanced Manufacturers (Sunday, October 13, 2024)
• SensiML Expands Platform Support to Include the RISC-V Architecture (Wednesday, October 9, 2024)
• Boosting Efficiency and Reducing Costs: Silvaco's Approach to Semiconductor Fabrication (Monday, October 7, 2024)
• South Korean AI IC Design Companies Shifting to Dual-Foundry Model with Both Samsung and TSMC (Thursday, October 3, 2024)
• Faraday Enhances 3D-IC Design Service with Ansys Multiphysics Analysis (Tuesday, October 1, 2024)
• Siemens brings industry leading Capital electrical and electronic systems design software to the cloud as a service (Sunday, September 29, 2024)
• SIAE Microelettronica Selects Ensilica as Key Partner to Design ASICs for Next-Generation Telecom Equipment (Wednesday, September 25, 2024)
• Boosting Efficiency and Reducing Costs: SilvacoÂ’s Approach to Semiconductor Fabrication (Tuesday, September 24, 2024)
• Silvaco Expands its Victory TCAD and Digital Twin Modeling Platform to Planar CMOS, FinFET and Advanced CMOS Technologies (Tuesday, September 24, 2024)
• SigmaSense Teams Up with Dolphin Design to Deliver Power Efficiency in their Advanced SDC300 Touch Controller (Monday, September 23, 2024)
• Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium (Sunday, September 22, 2024)
• Comcores and Extoll successfully completed the interoperability test of Comcores JESD204C IP core and Extoll SerDes PHY (Sunday, September 22, 2024)
• RAAAM Memory Technologies and NXP Semiconductors Announce Collaboration to Implement High Density On-Chip Memory (Sunday, September 22, 2024)