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• XConn Achieves First-Pass Silicon Success for CXL Switch SoC with Synopsys CXL and PCI Express IP Products (Wednesday, January 18, 2023)
• Analog Bits Awarded ISO 9001 and ASIL B Ready Certifications (Tuesday, January 17, 2023)
• Why Quantum Computing Capabilities Are Creating Security Vulnerabilities Today (Monday, January 16, 2023)
• Analog IPs Automate Integration, Tune to Fab Nodes (Sunday, January 15, 2023)
• Certus Semiconductor releases ESD library in GlobalFoundries 12nm Finfet process (Thursday, January 12, 2023)
• The Importance of 3D IC Ecosystem Collaboration (Wednesday, January 11, 2023)
• Chipletz selects Siemens' EDA solutions for its Smart Substrate IC packaging technology (Wednesday, January 11, 2023)
• Quantum Computing–Top Questions Answered (Tuesday, January 10, 2023)
• Semiconductor and Embedded Systems Architecture Labs (SEAL) makes new technology available to everyone for learning and innovation (Monday, January 9, 2023)
• Arteris Acquires Semifore to Accelerate System-on-Chip Development (Monday, January 9, 2023)
• Preparing engineering students with technology skills for the industrial world (Monday, January 9, 2023)
• Ceremorphic Introduces Custom Silicon Development for Advanced Nodes Using In-House Technology to Speed Customer HPC Chip Development (Monday, January 9, 2023)
• CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core Available For Licensing and Implementation from Global IP Core (Sunday, January 8, 2023)
• Digital Blocks AMBA Peripherals I3C, I2C, eSPI, xSPI Controller IP Core Families Extend Leadership with enhancements containing feature-rich, system-level integration features. (Sunday, January 8, 2023)
• Weebit Nano tapes-out first 22nm demo chip (Monday, January 2, 2023)
• Seven semiconductor trends for 2023 (Sunday, January 1, 2023)
• USB 3.0 IP, MIPI D-PHY v1.2 IP, Display Port v1.4 IP, 1G Ethernet IP, the Best-Selling Interface IP Cores solutions through T2M in 2022 (Sunday, January 1, 2023)
• Digital Blocks DMA Controller Verilog IP Core Family Extends Leadership with enhancements to AXI4 Memory Map and Streaming Interfaces (Sunday, January 1, 2023)
• Taiwan Brings 96 Startups to Attend CES 2023 (Wednesday, December 28, 2022)
• €270m for RISC-V chiplets to build European exascale supercomputers (Wednesday, December 28, 2022)
• Quantum Computing Brings New Error Correction Challenges (Sunday, December 25, 2022)
• Cadence Announces Industry Best-In-Class 8533Mbps LPDDR5X IP Solution for Next-Generation AI, Automotive and Mobile Applications (Sunday, December 25, 2022)
• GbE (10/100/1000Base-T) PHY IP Core, a robust, low-power, fully featured IP Core along with MAC Controller IP Core is available for immediate licensing (Monday, December 19, 2022)
• DDMA, multi-channel DMA Controller IP core from DCD-SEMI (Wednesday, December 14, 2022)
• M3 Technology Receives EE Awards for Simplifying Supercapacitor Designs (Tuesday, December 13, 2022)
• JEDEC Publishes Automotive Solid State Drive (SSD) Device Standard (Tuesday, December 13, 2022)
• Cadence Wins Six 2022 TSMC OIP Partner of the Year Awards (Monday, December 12, 2022)
• Faraday Unveils SONOS eFlash Platform with Infineon on UMC 40uLP (Monday, December 12, 2022)
• Sofics joins the Intel Foundry Services (IFS) Accelerator IP Alliance program (Sunday, December 11, 2022)
• USB 3.2 OTG Controller and PHY IP Cores for ultra-high speed, lossless data and power delivery are available for immediate licensing (Sunday, December 11, 2022)
• Finland connects a quantum computer to a supercomputer (Monday, December 5, 2022)
• France's Siquance startup targets 'European' quantum computing (Monday, December 5, 2022)
• Avery Design Systems Announces SimXACT-SA™ for Improved Sequential X-Verification (Monday, December 5, 2022)
• Ansys Announces GlobalFoundries Certification of Semiconductor Tools for GF 22FDX® Platform (Sunday, December 4, 2022)
• Implement seamless DRAM processing speeds utilizing Silicon Proven DDR4/LPDDR4/DDR3L Combo PHY IP Core in 12FFC process technology (Sunday, December 4, 2022)
• Innovative ASIC CPU Drives Record-Setting Server Performance (Sunday, December 4, 2022)
• Siemens streamlines medical standards compliance for Linux OS based systems (Wednesday, November 30, 2022)
• QuantWare launches Foundry Services for superconducting quantum chips (Monday, November 28, 2022)
• The MOSIS Service of the USC Information Sciences Institute and SkyWater Collaborate on Silicon IC Design Enablement and Manufacturing Service (Monday, November 28, 2022)
• Tachyum Successfully Runs LINPACK on FPGA With IEEE 754-2019 Compliant FPU (Monday, November 28, 2022)
• Truechip Announces First Customer Shipment of UCIe Verification IP (Monday, November 28, 2022)
• Faraday FPGA-Go-ASIC™ Succeeds in Penetrating the Market (Monday, November 21, 2022)
• Embrace the new age of ultra-high-definition multimedia with HDMI 2.0 Rx PHY IP Cores in 12FFC process technology with matching controller (Sunday, November 20, 2022)
• Truechip Announces First Customer Shipment of MIPI A-PHY Verification IP (Wednesday, November 16, 2022)
• Synopsys To Play A Key Role In Enabling Intel Foundry Services For US DOD Chip Program (Wednesday, November 16, 2022)
• StarFive Releases StarFive StarStudio IDE, which supports both Linux and Baremetal Development (Monday, November 14, 2022)
• Arasan announces MIPI CSI IP for FPGA supporting full C-PHY 2.0 speeds (Sunday, November 13, 2022)
• ZeroPoint Technologies can reduce data center energy consumption by 25% (Sunday, November 13, 2022)
• JEDEC Announces Publication of the SPD5118 Hub and Serial Presence Detect Device and the DDR5 SPD Contents Specifications (Sunday, November 13, 2022)
• Marvell Announces Innovative CXL Development Platform for Multi-Host Memory Pooling (Sunday, November 13, 2022)