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• CXL™ Consortium and JEDEC® Sign MOU Agreement to Advance DRAM and Persistent Memory Technology (Wednesday, August 24, 2022)
• Diakopto Unveils PrimeX™ - Revolutionary EDA Solution for Top-Hierarchy Power Grid and Signal Net EM/IR (Sunday, August 21, 2022)
• Augment your Peripheral slot's performance with the Low Power and High Throughput PCIe 4.0 PHY IP Cores in 12FFC with matching PCIe 4.0 Controller IP Cores (Sunday, August 21, 2022)
• JEDEC Updates Universal Flash Storage (UFS) and Supporting Memory Interface Standard (Wednesday, August 17, 2022)
• Efinix Low Power, Small Footprint FPGA Selected for SPRESENSE Development Platform (Tuesday, August 16, 2022)
• Truechip Announces First Customer Shipment of CXL 3 Verification IP and CXL Switch Model (Thursday, August 11, 2022)
• Arasan refreshes its Total USB IP Solution with its next generation of USB 2.0 PHY IP (Wednesday, August 10, 2022)
• Siemens selected by Microsoft for Rapid Assured Microelectronics Prototypes (RAMP) Program (Tuesday, August 9, 2022)
• Enhance your SD Card experience by integrating SD 4.1 UHS-II PHY IP Core to achieve Ultra High Speeds (Sunday, August 7, 2022)
• Space Codesign Systems joins Siemens Digital Industries Software Solution Partner Program as a Software and Technology Partner (Sunday, August 7, 2022)
• Cadence Accelerates Hyperscale SoC Design with Industry's First Verification IP and System VIP for CXL 3.0 (Thursday, August 4, 2022)
• Cadence Library Characterization Solution Accelerates Delivery and Enhances Quality of Arm Memory Products (Wednesday, August 3, 2022)
• Accellera Announces Proposed Working Group to Explore Clock Domain Crossing Standard (Tuesday, August 2, 2022)
• CXL Consortium Releases Compute Express Link 3.0 Specification to Expand Fabric Capabilities and Management (Tuesday, August 2, 2022)
• UCIe™ (Universal Chiplet Interconnect Express™) Consortium Announces Incorporation and New Board Members; Open for Membership (Tuesday, August 2, 2022)
• Avery Design Announces CXL 3.0 VIP (Monday, August 1, 2022)
• CXL Consortium and OpenCAPI Consortium Sign Letter of Intent to Transfer OpenCAPI Specifications to CXL (Monday, August 1, 2022)
• Mobiveil and Avery Design Systems Extend Partnership to Accelerate Design and Verification of NVMe 2.0-Enabled SSD Development (Monday, August 1, 2022)
• Avery Design Systems Verification IP Helps Solid State Storage Controller Startup Validate its Designs and Get to Market Faster (Sunday, July 31, 2022)
• Faraday Unveiled FPGA-Go-ASIC Prototyping Platform to Accelerate FPGA-to-ASIC Conversion (Wednesday, July 27, 2022)
• MIPI UniPro v2.0 Doubles Peak Data Rate and Delivers Greater Throughput and Reduced Latency for Flash Memory Storage Applications (Tuesday, July 26, 2022)
• CFX announces commercial availability of anti-fuse OTP technology on 55nm CIS process (Sunday, July 24, 2022)
• In-house software team provides Sondrel with a key advantage for its turnkey ASIC service of turning concept into silicon (Monday, July 18, 2022)
• Vidatronic Expands FinFET Portfolio with 7 nm to 4 nm FlexGUARD™ and Power Quencher® Intellectual Properties (IPs) Available for Licensing (Monday, July 18, 2022)
• 10Gbps！The fastest LPDDR5/5X IP deliver production ! (Sunday, July 17, 2022)
• MIPI RFFE Master & Slave Controller IP Cores to control your complex RF-Front End Interfaces (Sunday, July 17, 2022)
• Siemens' Calibre platform expands early design verification solutions (Tuesday, July 12, 2022)
• Truechip Introduces Automation Products - NoC Verification and NoC Performance - for Revolutionizing the Verification Spectrum (Monday, July 11, 2022)
• Dutch Startup on the Way to Make Quantum Photonic Processors Real (Monday, July 11, 2022)
• Siemens' state-of-the-art Symphony Pro platform expands mixed signal IC verification capabilities (Sunday, July 10, 2022)
• Agile Analog announces IR Drop Sensor IP (Sunday, July 10, 2022)
• Agile Analog announces RC Oscillator IP (Sunday, July 10, 2022)
• Cadence Introduces the Voltus-XFi Custom Power Integrity Solution, Delivering over 3X Productivity Gains (Thursday, July 7, 2022)
• Brite Semiconductor Introduces Two Innovative Technologies For DDR PHY (Wednesday, July 6, 2022)
• Outsourcing Supply Chain Management for chip manufacture can increase yields and quality (Tuesday, July 5, 2022)
• proteanTecs to Showcase Deep Data Analytics at DAC and SEMICON West 2022 (Tuesday, July 5, 2022)
• Multiport Memory With Analog Port Patent Issued (Monday, July 4, 2022)
• Ludicrous Low Power (L2P) by SILICONGATE (Monday, July 4, 2022)
• Ultra-low power memory targets the metaverse (Monday, July 4, 2022)
• Enhance your High-Density data processing capabilities to new heights with the USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP Core interface in 28HPC+/HPC process technology (Sunday, July 3, 2022)
• Truechip Adds USB 4 Hub Model & USB 4 Retimer Model to its Verification IP Portfolio (Wednesday, June 29, 2022)
• Multiport Memory With Analog Port Patent Issued (Wednesday, June 29, 2022)
• Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success (Tuesday, June 28, 2022)
• Siemens launches Siemens Xcelerator - an open digital business platform to accelerate digital transformation (Tuesday, June 28, 2022)
• Enhanced Serial Peripheral Interface (eSPI) Master/Slave Controller (Monday, June 27, 2022)
• Brite Launches High-Precision 16 bit SAR ADC (Wednesday, June 22, 2022)
• CFX announces commercial availability of anti-fuse OTP technology on 90nm CIS process (Wednesday, June 22, 2022)
• Expedera Expands Global Reach with New Regional Design Centers and Chinese Langauge Website (Monday, June 20, 2022)
• Complete UFS 3.1 Controller solution (Analog / Digital IP Cores) licensed to China's leading Smartphone Company (Sunday, June 19, 2022)
• Alchip Technologies Offers 3nm ASIC Design Services (Wednesday, June 15, 2022)