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• ARIES Embedded Presents New MCXL Reference IP Design (Wednesday, March 30, 2022)
• Faraday Launches Cortex-A53-based Platform to Accelerate FinFET SoC Development (Wednesday, March 30, 2022)
• M31 Speeds Delivery of Silicon IP by 5X Using the Cadence Library Characterization Solution in the Cloud (Wednesday, March 30, 2022)
• Synopsys Launches Industry's First Broad-Scale Cloud SaaS Solution to Transform Chip Development Landscape (Tuesday, March 29, 2022)
• Advancing VHDL's Verification Capabilities with VHDL-2019 Protected Types (Monday, March 28, 2022)
• Edgewater Wireless selects CMC Microsystems as fabrication services Partner (Monday, March 28, 2022)
• Introducing DDR5/DDR4/LPDDR5 Combo PHY IP Core, Silicon Proven in 12FFC for Next-Gen High performance SoCs is available for immediate licensing (Sunday, March 27, 2022)
• O-RAN Fronthaul Transport Subsystem is now available (Wednesday, March 23, 2022)
• CEA and Startup C12 Join Forces to Develop Next-Generation Quantum Computers with Multi-Qubit Chips at Wafer Scale (Wednesday, March 23, 2022)
• Cadence Selected by Microsoft for RAMP Phase II Program (Wednesday, March 23, 2022)
• Avalanche Technology and Efabless Partner for System-On-Chip Development using Google's Open-Source Program (Monday, March 21, 2022)
• Intrinsic ID Optimizes SRAM PUF Security Technology for Advanced Process Nodes with QuiddiKey 4.x (Wednesday, March 16, 2022)
• Xylon Demonstrates Hot Swapping of Programmable FPGA/SoC Chip Parts (Wednesday, March 16, 2022)
• Synopsys Improves Interoperability Between CODE V and LightTools (Monday, March 14, 2022)
• OPENEDGES Announces Silicon Proven 12nm LPDDR54 PHY IP (Wednesday, March 9, 2022)
• Zepp Health signs licence agreement for sureCore's EverOn ultra-low voltage memory IP (Wednesday, March 9, 2022)
• Arasan announces the immediate availability of its MIPI D-PHY IP as Tx Only or Rx Only for the GlobalFoundries 12nm FinFET process node (Tuesday, March 8, 2022)
• PCIe 5.0 SerDes PHY and Controller IP Cores for all High-End Serial connect Interfaces in advanced SoCs is available for immediate licensing (Sunday, March 6, 2022)
• Synopsys Extends OptoCompiler Support for New GF Fotonix Platform (Sunday, March 6, 2022)
• Agile Analog's Approach to Analog IP Design and Quality — Why "Silicon Proven" is NOT What You Think (Thursday, March 3, 2022)
• Dolphin Design chooses DEFACTO's SoC Compiler 9.0: a turnkey methodology to reduce project costs and increase team efficiency (Wednesday, March 2, 2022)
• Sondrel explains the 10 steps to model and design a complex SoC (Tuesday, March 1, 2022)
• USB 3.1 Device & Host Controller IP Cores with highly configurable design for Superspeed data transfers in all kinds of advanced SoCs is available for immediate licensing (Sunday, February 27, 2022)
• Cadence and Dassault Systemes Partner to Transform Electronic Systems Development (Wednesday, February 23, 2022)
• We are now AS 9100D certified! - Logic Fruit Technologies (Sunday, February 20, 2022)
• MIPI D-PHY Tx IP Core in 22nm along with MIPI DSI-2 Tx Controller IP Core for your High-End Camera and Display needs is available for immediate licensing (Sunday, February 20, 2022)
• Faraday Succeeds in Factory Automation ASIC (Wednesday, February 16, 2022)
• Berkeley Lab Unveils ASIC Chip Failure Bypass System (Wednesday, February 16, 2022)
• Synopsys to enable secure software development (Sunday, February 13, 2022)
• SMIC Outpaces Rivals on Strong Local Demand (Saturday, February 12, 2022)
• Sondrel's IP platforms prevent operational chip errors as Functional Safety is built in (Tuesday, February 8, 2022)
• Synopsys Introduces Code Sight Standard Edition to Enable Secure Software Development (Tuesday, February 8, 2022)
• sureCore announces technology for in-memory computing (Monday, February 7, 2022)
• USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP in 12nm, 16nm and 22nm process nodes with simple integration and flexible customization is ready for immediate licencing for your advanced SoC design (Sunday, February 6, 2022)
• GOWIN Semiconductor USB 2.0 PHY Interface and Device Controller IPs Achieve USB-IF Certification (Sunday, January 30, 2022)
• Logic Design Solutions Launches NVME Host IP on Xilinx Ultrascale & Ultrascale Plus FPGA (Thursday, January 27, 2022)
• Pearl Semi selects Siemens' Symphony AMS platform for its novel low-noise digital PLL design (Wednesday, January 26, 2022)
• JEDEC Publishes HBM3 Update to High Bandwidth Memory (HBM) Standard (Wednesday, January 26, 2022)
• Thalia launches next generation IP reuse tools for smarter, more agile semiconductor product development (Tuesday, January 25, 2022)
• Rambus Delivers PCIe 6.0 Controller for Next-Generation Data Centers (Tuesday, January 25, 2022)
• CFX announces commercial availability of anti-fuse OTP technology on 55nm Logic process (Monday, January 24, 2022)
• Weebit Nano demonstrates its first crossbar ReRAM arrays (Sunday, January 23, 2022)
• Cadence Palladium Z2 Enterprise Emulation Platform Accelerates Microchip's Data Center Solutions SoC Development (Wednesday, January 19, 2022)
• L&T Technology Services wins USD45 million EV deal from U.S. Auto Tier-1 (Monday, January 17, 2022)
• EnSilica and Omni Design Collaborating on Multiple SoCs (Monday, January 17, 2022)
• Airbus Selects Siemens Capital Software for E/E Systems Development (Monday, January 17, 2022)
• MIPI UFS 3.1, M-PHY 4.1, Unipro 1.8, ONFi 4.1 and many more IP Cores are available for immediate licensing for your advanced UFS Device Applications as a complete bundled solution (Sunday, January 16, 2022)
• PCI-SIG Releases PCIe 6.0 Specification Delivering Record Performance to Power Big Data Applications (Tuesday, January 11, 2022)
• Reinventing Traceability: Adding domain intelligence with Arteris Harmony Trace (Tuesday, January 11, 2022)
• Sondrel explains the vital coordinating role of Systems Architects (Monday, January 10, 2022)