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• Marvell Extends Data Infrastructure Leadership with TSMC 3nm Platform (Tuesday, October 5, 2021)
• Siemens introduces mPower power integrity solution for analog, digital and mixed-signal IC designs (Monday, September 27, 2021)
• Synopsys Achieves AIM Photonics Certification (Sunday, September 26, 2021)
• SiPearl opens design centre in Grenoble, looks for 50 engineers (Sunday, September 26, 2021)
• Cadence Accelerates Development of Mobile, Automotive and Hyperscale Systems with the Helium Virtual and Hybrid Studio (Wednesday, September 22, 2021)
• Samsung Foundry Certifies Synopsys PrimeLib Unified Library Characterization and Validation Solution at 5nm, 4nm and 3nm Process Nodes (Tuesday, September 21, 2021)
• Codasip Opens UK Design Center led by Simon Bewick (Monday, September 20, 2021)
• Cadence Collaborates with GlobalFoundries to Qualify Pegasus Verification System for 12LP/12LP+ and 22FDX™ Technologies (Tuesday, September 14, 2021)
• Siemens' Aprisa place-and-route solution now certified for GlobalFoundries' 22FDX platform (Tuesday, September 14, 2021)
• SmartDV Provides Broad Portfolio of Memory Modeling, Design and Verification Solutions (Monday, September 13, 2021)
• Synopsys PrimeSim Reliability Analysis Solution Accelerates Design of Hyper-Convergent ICs for Mission-Critical Applications (Sunday, September 12, 2021)
• EnSilica opens new design centre, starts recruitment drive (Tuesday, September 7, 2021)
• Cadence and Samsung Accelerate 3nm Mixed-Signal Silicon (Tuesday, September 7, 2021)
• VisualSim Cloud brings popular System-Level Modeling Solution to the Browser (Monday, September 6, 2021)
• EPFL launches quantum computing and technology centre (Monday, August 30, 2021)
• Photonic Chips for Fault-Tolerance Quantum Computing (Monday, August 30, 2021)
• eTopus Selects Diakopto's ParagonX Platform for Ultra-High Speed SerDes IP (Monday, August 23, 2021)
• Synopsys Enables First-Pass Silicon Success for Achronix's New FPGA for Data and AI Acceleration Applications (Monday, August 23, 2021)
• Quantum Computing Technologies Highlight CMC Microsystems' Plan to Accelerate High Tech Manufacturing in Canada (Monday, August 23, 2021)
• Imec and Xanadu engage in SiN (Tuesday, August 17, 2021)
• Picocom Accelerates 5G Communications SoC Development with Cadence Palladium Emulation (Tuesday, August 17, 2021)
• Xpeedic EDA Cloud Platform on Microsoft Azure (Monday, August 16, 2021)
• Rambus HBM subsystem more than doubles HBM2E speed (Sunday, August 15, 2021)
• Sondrel creates unique modelling flow software to cut ASIC modelling time from months to a few days (Monday, August 9, 2021)
• Semiconductor Industry 2.0 (Monday, August 9, 2021)
• Tessent boosts simultaneous analysis of hardware and software in SoC designs (Thursday, July 22, 2021)
• Cadence and UMC Collaborate on 22ULP/ULL Reference Flow Certification for Advanced Consumer, 5G and Automotive Designs (Monday, July 12, 2021)
• Corigine Delivers a Next-Generation Prototyping System for ASIC and Pre-Silicon Software Development (Tuesday, July 6, 2021)
• Silicon Creations Selects Diakopto's ParagonX IC Debugging Platform (Tuesday, June 29, 2021)
• AnalogX Accelerates Time-to-Market with Diakopto's ParagonX Debugging Platform and Methodology (Tuesday, June 29, 2021)
• Dialog Semiconductor Expands AC/DC Portfolio, Targeting High Power Density PSUs with Zero Voltage Switching Technology (Monday, June 28, 2021)
• GUC Tapes Out AI/HPC/Networking Platform on TSMC CoWoS Technology (Tuesday, June 22, 2021)
• Alphawave IP Adopts Diakopto's ParagonX EDA Platform and Methodology (Monday, June 21, 2021)
• Imec demoes integrated forksheet FETs for 2nm processes (Wednesday, June 16, 2021)
• CEA-Leti Collaborates with Siemens to Launch Process Design Kit that Supports Multiple Technologies, Simplifies Creation of Optical Circuits (Wednesday, June 16, 2021)
• Thalia Design Automation partners with Sofics to enhance offering for analog circuit and IP reuse (Tuesday, June 15, 2021)
• Siemens Enhances Nucleus ReadyStart for Arm Platforms (Wednesday, June 9, 2021)
• New Cadence Allegro X Design Platform Revolutionizes System Design (Tuesday, June 8, 2021)
• Siemens acquires proFPGA product family from PRO DESIGN to expand industry-leading IC verification portfolio (Monday, June 7, 2021)
• Siemens EDA Tools Now Qualified on TSMC's N3, N4 Processes (Sunday, June 6, 2021)
• Aldec Launches HES-DVM Proto "Cloud Edition" - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping (Tuesday, June 1, 2021)
• TSMC Technology Symposium: Siemens verification for TSMC 4nm and 3nm (Tuesday, June 1, 2021)
• Cadence Unleashes Clarity 3D Solver on the Cloud for Straightforward, Secure and Scalable Electromagnetic Analysis of Complex Systems on AWS (Tuesday, May 25, 2021)
• Imperas Simulation Reference Models selected by IAR Systems for Arm 64bit (Tuesday, May 25, 2021)
• PLDA Announces XpressRICH PCI Express 6.0 Controller IP for Next Generation SoC Designs (Monday, May 24, 2021)
• Avery Design Launches PCI Express 6.0 Verification IP to Enable Early Development, Compliance Checking for New Version of Standard (Monday, May 24, 2021)
• Thalia's AMALIA Technology Analyzer de-risks Analog IP reuse for major IP houses and IC manufacturers (Monday, May 17, 2021)
• Synopsys unveils breakthrough in emulation performance (Monday, May 17, 2021)
• Sondrel's latest reference IP platform enables ultra-powerful signal and data processing SoCs to be created faster for lower costs (Sunday, May 9, 2021)
• Synopsys Delivers Enhanced Memory Design Productivity to Nanya Technology (Tuesday, May 4, 2021)