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• Synopsys Collaborates with TSMC to Accelerate 3nm Innovation, Enabling Next-Generation SoC Design (Monday, August 24, 2020)
• Synopsys and TSMC Accelerate 2.5D/3DIC Designs with Chip-on-Wafer-on-Substrate and Integrated Fan-Out Certified Design Flows (Monday, August 24, 2020)
• NSITEXE Adopts Synopsys HAPS Prototyping to Validate Data Flow Processor IP (Tuesday, August 18, 2020)
• Moortec Provides In-Chip Sensing Fabrics on TSMC N6 Process Technology (Tuesday, August 18, 2020)
• S2C and Mirabilis Design Teamup to Deliver a Heterogeneous Solution for SoC Architecture Exploration and Verification (Monday, August 17, 2020)
• Nuvoton Accelerates the Development of its MCU Designs with the Cadence Palladium Z1 Enterprise Emulation Platform (Monday, August 17, 2020)
• SiFive Announces OpenFive, an Industry-Leading Custom Silicon Business Unit (Sunday, August 16, 2020)
• Synopsys Introduces Integrated Electric Vehicle Virtual Prototyping Solution (Wednesday, August 12, 2020)
• Truechip Announces Customer Shipment Of USB4 And eUSB Verification IPs (Sunday, August 9, 2020)
• Intento Design announces the launch of ID-Calibre, an ID-Substrate extension for behavioural TCAD simulation on a complete AMS chip (Wednesday, July 29, 2020)
• Marvell Unveils the Industry's Most Comprehensive Custom ASIC Offering (Monday, July 27, 2020)
• Cadence and UMC Certify mmWave Reference Flow on 28HPC+ Process for Advanced RF Designs (Wednesday, July 22, 2020)
• Carlos Mazure, EVP of Soitec and Chairman of the SOI Industry Consortium, Joins Silvaco Board of Directors (Wednesday, July 22, 2020)
• Alchip Technologies 7nm ASIC Capabilities Set Advanced Technology Pace (Tuesday, July 21, 2020)
• GLOBALFOUNDRIES Partners with Synopsys, Mentor, and Keysight on Interoperable Process Design Kit (iPDK) Support for 22FDX (Tuesday, July 21, 2020)
• CFI funding fuels new services for researchers from CMC and CNDN (Monday, July 20, 2020)
• Mirabilis Design announces the first Application-Specific University Program (Wednesday, July 8, 2020)
• SmartDV Broadens Support for Arm AMBA Protocol with Verification IP Solutions for AMBA CHI, CXS, LPI (Tuesday, July 7, 2020)
• JLQ Technology Selects Synopsys DesignWare IP to Accelerate Development of Next-Generation SoCs (Monday, July 6, 2020)
• Synopsys and Arm Extend Strategic Partnership to Deliver Superior Full-Flow Quality-of-Results and Time-to-Results (Sunday, June 28, 2020)
• Synopsys Collaboration with Samsung Foundry Enables Rollout of Samsung SAFE Cloud Design Platform (Wednesday, June 17, 2020)
• Samsung Provides One-Stop Foundry Design Environment with the Launch of 'SAFE™ Cloud Design Platform' (Tuesday, June 16, 2020)
• Cadence Collaborates with TSMC and Microsoft to Reduce Semiconductor Design Timing Signoff Schedules with the Cloud (Monday, June 15, 2020)
• Agile Analog and EnSilica Collaborate to Improve Quality and Reliability of Microchips (Monday, June 15, 2020)
• Truechip Announces Shipping of Performance Analyzer Tool Kit to Aaroh Labs (Wednesday, June 10, 2020)
• Moortec Launches New In-Chip Technology for Highly Distributed, Real-Time Thermal Analysis on TSMC N5 Process (Tuesday, June 9, 2020)
• SmartDV's Design and Verification Solutions Portfolio Surpasses 600 Offerings (Monday, June 8, 2020)
• Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies (Tuesday, June 2, 2020)
• UltraSoC enables ultra-high-speed closed-chassis analytics and debug over Synopsys USB3 (Monday, June 1, 2020)
• GigaDevice GD32 MCU and Amazon AWS Launch New Embedded Cloud Platform (Monday, June 1, 2020)
• Synopsys Announces Support of TensorFlow Lite for Microcontrollers on Energy-Efficient ARC EM and ARC HS Processor IP (Tuesday, May 26, 2020)
• Cadence to Optimize Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development (Tuesday, May 26, 2020)
• Synopsys Enables Tapeout Success for Early Adopters of Arm's Next Generation of Mobile IP (Monday, May 25, 2020)
• S2C Announces New Prodigy Cloud System for Next Generation SoC Prototyping (Wednesday, May 20, 2020)
• Cadence Delivers 10 New Verification IP Targeting Automotive, Hyperscale Data Center and Mobile Applications (Monday, May 18, 2020)
• SmartDV Ships First Design and Verification IP for MIPI RFFE v3.0 Specification (Monday, May 11, 2020)
• Faraday's SoCreative!V Platform Accelerates SoC Development in Edge Applications (Monday, May 4, 2020)
• Dolphin Design unveils its innovative Energy Efficient Platforms, complete turnkey solutions for competitive SoC designs (Sunday, May 3, 2020)
• Khronos Group Releases OpenCL 3.0 (Monday, April 27, 2020)
• Synopsys Introduces 3DIC Compiler, Industry's First Unified Platform to Accelerate Multi-die System Design and Integration (Monday, April 27, 2020)
• Mirabilis Design is making the standard training class on Model-based System Simulation and Electronic System-Level Design for free (Monday, April 6, 2020)
• Veriest International On-line Verification Meetup (Monday, March 30, 2020)
• SiFive Selects Synopsys Fusion Design Platform and Verification Continuum Platform to Enable Rapid SoC Design (Tuesday, March 24, 2020)
• InterMotion Technology boosts IP verification productivity for Lattice Semiconductor's CrossLink FPGA family using Aldec's Active-HDL (Monday, March 23, 2020)
• Faraday Delivers System-Level ESD Protection Service to Reduce ASIC Time-to-Market (Monday, March 16, 2020)
• Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput (Monday, March 16, 2020)
• SiFive Launches Advanced Trace and Debug Portfolio, SiFive Insight (Monday, March 16, 2020)
• Synopsys Unveils RTL Architect To Accelerate Design Closure (Sunday, March 15, 2020)
• Synopsys Custom Design Platform Secures Full-flow Displacement of Legacy Design Tools at Alphawave (Monday, March 9, 2020)
• Faraday Announces Low-DPPM Solution for a Wide Range of ASIC Applications (Wednesday, March 4, 2020)