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• UMC certifies Mentor product lines for its new 22nm ultra-low-power process technology (Wednesday, March 4, 2020)
• Defacto Announces STAR 8.0 and Provides a Unified "All-in-One" SoC Design Solution to Help Conciliating Between RTL, IP-XACT, UPF, SDC, and Physical Design Information (Tuesday, March 3, 2020)
• Veriest contributes to the verification of Nuvoton's Computing MCU devices (Tuesday, March 3, 2020)
• Gowin Semiconductor Adds Ubuntu Support to their Gowin EDA FPGA Software for Improved Artificial Intelligence and IoT Development Toolchain Integration (Wednesday, February 19, 2020)
• Synopsys' Fusion Compiler Adopted by AMD (Tuesday, February 18, 2020)
• SmartDV Offers New Design IP for DDR5 and LPDDR5 (Monday, February 17, 2020)
• UltraSoC collaborates with PDF Solutions to prevent in-life product failures using end-to-end analytics and advanced machine learning techniques (Wednesday, February 12, 2020)
• SmartDV Adds Support for MIPI I3C 1.1 Across Entire IP Portfolio (Tuesday, February 11, 2020)
• SmartDV Achieves Record Revenue in 2019 (Monday, February 3, 2020)
• Imagination Technologies expands with new design centre in Romania (Wednesday, January 15, 2020)
• Cadence Expands Collaboration with Broadcom for 5nm and 7nm Designs (Monday, January 13, 2020)
• NEC Selects Synopsys ZeBu Server 4 Emulation Solution for Super Computer Verification (Thursday, December 19, 2019)
• Codasip Studio and Codasip CodeSpace 8.2 available (Sunday, December 15, 2019)
• INSPECTOR™ diagnostic and debug platform passed the PCIe 4.0 compliance (Monday, December 9, 2019)
• NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications (Monday, December 9, 2019)
• SmartDV's TileLink, Verilator VIP on Full Display at RISC-V Summit (Tuesday, December 3, 2019)
• D&R announces the opening of an IP Core Store to support Soft IP Cores sales to the Chinese market (Monday, December 2, 2019)
• Moortec's In-Chip Monitoring Subsystem Supports Uhnder in Groundbreaking Digital Automotive Radar-on-Chip (Sunday, December 1, 2019)
• SmartDV's Platform-Independent VIP Portfolio Ensures Seamless Coverage-Driven Verification Flow (Wednesday, November 20, 2019)
• EasyIC Design joins Arm Approved Design Partner Program (Monday, November 18, 2019)
• SmartDV to Exhibit at SemIsrael Expo, ICCAD China 2019 (Wednesday, November 6, 2019)
• Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis (Tuesday, November 5, 2019)
• Mentor boosts 64-bit Arm-based server platform by enabling Arm architecture support for Questa simulation tools (Monday, October 7, 2019)
• IC'Alps joins Arm Approved Design Partner program to better support customers with ASIC development (Monday, October 7, 2019)
• Dream Chip Technologies joined Samsung Foundry's Design Solution Partner (DSP) Program (Monday, October 7, 2019)
• HDL Design House Appoints Frank Werner as Worldwide Sales Director (Monday, September 30, 2019)
• SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator (Monday, September 30, 2019)
• Gen-Z Physical Layer Specification 1.1 now available for download (Sunday, September 29, 2019)
• Veriest kick-starts Formal Verification methodology at Valens (Tuesday, September 17, 2019)
• SmartDV Announces Availability of Ethernet TSN Design IP (Monday, September 16, 2019)
• SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India (Tuesday, September 10, 2019)
• sureCore Unveils Low Power Design Service (Monday, August 26, 2019)
• SmartDV to Exhibit at OpenPower Summit August 19-20 (Tuesday, August 13, 2019)
• Tessolve Highlights Test Engineering Practices, Participating At The ITC India 2019 As Platinum Sponsors (Tuesday, July 30, 2019)
• Cadence Delivers Portable Test and Stimulus Methodology and Library (Tuesday, July 16, 2019)
• Arm Flexible Access gives chip designers the freedom to experiment and test before they invest (Monday, July 15, 2019)
• Tower Semiconductor : TowerJazz, Cadence and Lumerical Deliver Silicon-Photonics and SiGe- Integrated PDK with a Complete Optical Transceiver Design Environment (Tuesday, July 9, 2019)
• Cadence Announces First-to-Market DisplayPort 2.0 Verification IP (Tuesday, June 25, 2019)
• Mentor's new Calibre Recon functionality methodically analyzes "early draft" IC designs for faster verification (Tuesday, May 28, 2019)
• Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development (Monday, May 27, 2019)
• Synopsys and Arm Extend Collaboration to Fusion Compiler to Accelerate Implementation of Arm's Next-Generation Client and Infrastructure Cores (Monday, May 13, 2019)
• eSilicon Tapes Out 7nm Combo PHY (HBM2/HBM2E/Low Latency) Test Chip (Wednesday, May 8, 2019)
• SmartDV Heads to ChipEx2019 in Israel with Extensive Design and Verification IP Portfolio (Monday, May 6, 2019)
• Synopsys Announces Industry's First DDR5 NVDIMM-P Verification IP for Next-generation Storage-class Memory Designs (Tuesday, April 30, 2019)
• Moortec Provide Embedded Monitoring Solutions for Arm's Neoverse N1 System Development Platform on TSMC 7nm Process Technology (Tuesday, April 30, 2019)
• Moortec To Showcase Its PVT Monitoring IP At TSMC 2019 Boston Technology Workshop (Monday, April 29, 2019)
• Moortec to Showcase its PVT Monitoring IP at TSMC 2019 Technology Symposium (Tuesday, April 16, 2019)
• SmartDV's DVCon China Exhibit to Showcase Extensive Verification IP Portfolio (Tuesday, April 9, 2019)
• Cadence Eyes System Analysis Market (Monday, April 1, 2019)
• UltraSoC demonstrates advanced multicore debug at Embedded World 2019 (Monday, February 25, 2019)