Search News

Design Platform News

• ARM edges closer to full 2nm chip designs with Total Design (Tuesday, October 17, 2023)
• GOWIN Semiconductor Expands its GW1NZ Series of Low-Cost, Small-Size, and Low-Power Devices (Sunday, October 15, 2023)
• OPENEDGES Extends Partnership with InnoGrit Corp for 6nm LPDDR5/4X/4 Memory Controller IP (Sunday, October 15, 2023)
• Credo Joins with Industry Players to Announce Effort to Standardize CXL Active Electrical Cables & Optics at OCP Global Summit 2023 (Wednesday, October 11, 2023)
• JEDEC and Open Compute Project Foundation Pave the Way for a New Era of Chiplet Innovation (Tuesday, October 10, 2023)
• Accellera Releases Portable Test and Stimulus Standard 2.1 (Monday, October 9, 2023)
• Siemens launches Tessent tool for Verilog and RTL design for test (Monday, October 9, 2023)
• TSMC looks to standardise chiplet protocols in "world changing" move (Sunday, October 8, 2023)
• ADTechnology and Zaram Technology to develop the next-generation of telecommunications semiconductor chips (Thursday, October 5, 2023)
• Marquee Semiconductor Joins Singapore Semiconductor Industry Association to Catalyze Development of Singaporean Hub (Wednesday, October 4, 2023)
• ELES and proteanTecs Partner to Enhance Reliability Testing with Deep Data Analytics (Wednesday, October 4, 2023)
• Tenstorrent Selects Samsung Foundry to Manufacture Next-Generation AI Chiplet (Wednesday, October 4, 2023)
• MachineWare announces new ARM processor simulation and SystemC profiling products, adds Windows support (Wednesday, October 4, 2023)
• TSMC's 3Dblox 2.0 and 3DFabric Alliance Achievements Set the Stage for the Future of 3D IC (Tuesday, October 3, 2023)
• CEA and Siemens collaborate on research to expand applications of Digital Twin for industry (Monday, October 2, 2023)
• GlobalFoundries and Microchip Announce Microchip's 28nm SuperFlash® Embedded Flash Memory Solution in Production (Tuesday, September 26, 2023)
• Cadence Custom/Analog Design Migration Flow Accelerates Adoption of TSMC Advanced Process Technologies (Monday, September 25, 2023)
• Flex Logix Expands Upon Industry-leading Embedded FPGA Customer Base (Sunday, September 24, 2023)
• Alphacore Recognized for its TID Results of 22-nm FDSOI SRAM Published in IEEE Transactions on Nuclear Science journal (Wednesday, September 20, 2023)
• UXL looks to standardise heterogeneous compute (Tuesday, September 19, 2023)
• Flex Logix Announces Reconfigurable Block RAM with ECC Option (Sunday, September 17, 2023)
• Marquee Semiconductor Achieves ISO 9001 Certification for Exemplary Management System (Tuesday, September 12, 2023)
• Alchip Collaborates With Arteris To Expand ASIC Design Services (Tuesday, September 12, 2023)
• VisualSim Secure Model Protector enables companies to collaborate in new product development (Tuesday, September 5, 2023)
• Toshiba sample software package expands microcontroller development tools ecosystem (Monday, September 4, 2023)
• Nextera-Adeas ST 2110 IP cores are now available on Intel FPGAs (Thursday, August 31, 2023)
• Cadence Collaborates with Arm to Accelerate Neoverse V2 Data Center Design Success with Cadence AI-driven Flows (Wednesday, August 30, 2023)
• Cadence Collaborates with Arm to Accelerate Neoverse V2 Data Center Design Success with Cadence AI-driven Flows (Tuesday, August 29, 2023)
• QuickLogic Unveils Customizable eFPGA IP on GlobalFoundries' 12LP Process (Monday, August 28, 2023)
• Racyics becomes Arm Approved Design Partner (Sunday, August 27, 2023)
• GDDR Does Math, Big-Screen Explosions (Wednesday, August 23, 2023)
• sureCore-Led CryoCMOS IP: Toward Scalable Quantum Computers (Wednesday, August 23, 2023)
• Creonic Engages in Numerous Research Projects within the 6G Platform (Wednesday, August 16, 2023)
• Marvell Introduces Industry's First 5nm Multi-Gigabit PHY Platform (Wednesday, August 16, 2023)
• Faraday Announces Infineon's SONOS eFlash is Fully Qualified on UMC's 40ULP Process (Wednesday, August 16, 2023)
• Sirius Wireless Partners with S2C on Wi-Fi6/BT RF IP Verification System for Finer Chip Design (Wednesday, August 16, 2023)
• Certus Semiconductor Partners with Pragma Design for Embedded ESD Detection Technology (Tuesday, August 15, 2023)
• CEVA Joins Samsung SAFE™ Foundry Program to Accelerate Chip Design for the Mobile, Consumer, Automotive, Wireless Infrastructure and IoT Markets (Sunday, August 13, 2023)
• Analog IP tackles side channel attacks (Monday, August 7, 2023)
• UCIe™ (Universal Chiplet Interconnect Express™) Consortium Releases its 1.1 Specification (Monday, August 7, 2023)
• Unlock seamless video transmission between graphics adapters and LCD displays with readily licensable, silicon-proven LVDS IP cores tailored for the advanced 22FDX process node (Sunday, August 6, 2023)
• DVB-C Demodulator IP Core Available For Immediate Implementation From Global IP Core (Sunday, August 6, 2023)
• JEDEC Publishes New Standard to Support CXL Memory Module Implementation (Tuesday, August 1, 2023)
• Renesas adopts Visual Studio IDE across entire range (Monday, July 31, 2023)
• Arm and industry leaders launch Semiconductor Education Alliance to address the skills shortage (Tuesday, July 25, 2023)
• Mobiveil and InPsytech Announce Successful Inter-Op Verification of Enterprise Flash Controller Design IP and ONFI 5.1 PHY IP (Monday, July 24, 2023)
• A methodology for turning an SoC into chiplets (Monday, July 24, 2023)
• 12bit 640Msps Dual-Channel IQ ADC High-Speed/High-Performance IP Cores for WiFi RF SoC is available for immediate licensing (Sunday, July 23, 2023)
• Cadence RTL design tool claims 5x faster RTL convergence (Sunday, July 23, 2023)
• The revolutionary potential of 3D IC technology in the semiconductor ecosystem (Thursday, July 20, 2023)