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• Apple completes its ARM lineup with 5nm, 134billion transistor M2 Ultra (Sunday, June 11, 2023)
• Imec's process technology roadmap to 2036 (Wednesday, June 7, 2023)
• Cadence expands Arm agreement for EDA tool verification (Tuesday, June 6, 2023)
• Marquee Semiconductor Acquires Semikunn Technology Services, Expanding Design Services Portfolio (Monday, June 5, 2023)
• Dolphin Design Selects Imperas for Processor Functional Design Verification (Sunday, June 4, 2023)
• Dolphin Design picks Imperas for processor functional verification (Sunday, June 4, 2023)
• Cadence Collaborates with Arm to Accelerate Mobile Device Silicon Success with New Arm Total Compute Solutions (Monday, May 29, 2023)
• Arm tapes out Cortex X4 on TSMC N3E (Monday, May 29, 2023)
• JESD204C PHY & Controller IP Cores with proven automotive compatibility are instantly licensable for extremely reliable performance for your SOC's (Sunday, May 28, 2023)
• Synopsys and Arm Strengthen Collaboration for Faster Bring-Up of Next-Generation Mobile SoC Designs on the Most Advanced Nodes (Sunday, May 28, 2023)
• SK hynix Enters Industry's First Compatibility Validation Process for 1bnm DDR5 Server DRAM (Sunday, May 28, 2023)
• Partnership enhances deep data analytics in SoCs (Thursday, May 25, 2023)
• Rambus's expectations on faster GDDR6 memory (Thursday, May 25, 2023)
• JEDEC Publishes Major Update to JEP30 PartModel Guidelines (Wednesday, May 24, 2023)
• Nanusens announces that it can now create ASICs with embedded sensors (Wednesday, May 24, 2023)
• Intel Launches Agilex 7 FPGAs with R-Tile, First FPGA with PCIe 5.0 and CXL Capabilities (Monday, May 22, 2023)
• PCI-SIG Certifies VectorPath Accelerator Card for PCIe Gen5 x16 @ 32 GT/s (Monday, May 22, 2023)
• USB 4.0 Host and Device Controller IP Cores unleashing the Power of High-Speed Connectivity with tunnelling of Display Port and PCIe is now available for Licensing (Sunday, May 21, 2023)
• NVIDIA Grace Drives Wave of New Energy-Efficient Arm Supercomputers (Sunday, May 21, 2023)
• CEVA and proteanTecs Announce Partnership to Optimize Reliability and Power of Complex SoCs (Sunday, May 21, 2023)
• K-Best MIMO Decoder IP Core Available For Immediate Integration From Global IP Core (Thursday, May 18, 2023)
• Arasan Announces immediate availability of its SUREBOOT™ Total xSPI PHY IP (Wednesday, May 17, 2023)
• Rambus and Socionext Renew Patent License Agreement (Wednesday, May 17, 2023)
• SiliconAlly: GigaPHY Testchip is back from Fabrication and Packaging (Wednesday, May 17, 2023)
• Arasan announces the immediate availability of its 2nd Generation MIPI D-PHY for GlobalFoundries 22nm SoC Designs (Tuesday, May 16, 2023)
• Weebit Nano to present recent ReRAM-based developments at the International Memory Workshop (IMW) 2023 (Tuesday, May 16, 2023)
• MIPI DevCon Returns to Silicon Valley to Explore MIPI in Automotive, IoT and Mobile (Tuesday, May 16, 2023)
• How Vehicle Design Is Influencing Processors (Monday, May 15, 2023)
• proteanTecs to Present in Open Compute Project (OCP) Webinar on Silent Data Errors for Resilient Data Centers (Sunday, May 14, 2023)
• CryoCMOS Consortium develops 4K & 77K transistor models to enable CryoIP development (Wednesday, May 10, 2023)
• OPENEDGES' 12nm LPDDR5/4x/4 PHY is Ready for Mass Production by Novachips' SSD (Tuesday, May 9, 2023)
• Cryo-IP for quantum computing (Tuesday, May 9, 2023)
• Quantinuum's H2 quantum computer described as a significant step forward (Tuesday, May 9, 2023)
• Launch of the New Horizon Europe Project SYCLOPS (Tuesday, May 9, 2023)
• TSMC Teams Up With EDA Companies to Speed Up Design Flows (Tuesday, May 2, 2023)
• PsiQuantum Expands Development Engagement and Plan for Production Ramp of Quantum Computing Technology at SkyWater's Minnesota Fab (Monday, May 1, 2023)
• Alps Alpine uses Siemens Symphony to verify mixed-signal touch chip (Monday, May 1, 2023)
• HDL Design House develops its first full SoC from architecture definition to tapeout for an external customer (Wednesday, April 26, 2023)
• Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox™ Standard (Wednesday, April 26, 2023)
• M31 demonstrates high-speed interface IP development achievements on TSMC's 7nm & 5nm process technologies (Wednesday, April 26, 2023)
• Fraunhofer IIS/EAS Selects Achronix Embedded FPGAs (eFPGAs) to Build Heterogeneous Chiplet Demonstrator (Tuesday, April 25, 2023)
• Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox™ Standard (Tuesday, April 25, 2023)
• High-precision microsensor technology for a wide application range (Tuesday, April 25, 2023)
• OPENEDGES' 12nm LPDDR5/4 Memory Subsystem IP that Drives Innovation Licensed by ASICLAND (Monday, April 24, 2023)
• Agile Analog launches innovative digitally wrapped analog IP subsystems (Monday, April 24, 2023)
• Synopsys and TSMC Collaborate to Jumpstart Designs on TSMC's N2 Process with Optimized EDA Flows (Monday, April 24, 2023)
• Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies (Monday, April 24, 2023)
• Introducing High-Speed Fractional PLL IP Cores with SSC that offers exceptional features in different process technologies (Sunday, April 23, 2023)
• Arm reportedly developing 'advanced' test chip for customers (Sunday, April 23, 2023)
• Omni Design's High Performance Analog Front Ends are Adopted in Socionext's Next Generation Communications SoCs (Saturday, April 22, 2023)