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Chiplet / Multi-Die News

• Lorentz Solution Joins Intel Foundry Services (IFS) Accelerator EDA Alliance Program to Enable Peakview EM Platform and Accelerate IC and 3DIC Designs (Wednesday, February 8, 2023)
• Rambus Delivers 6400 MT/s DDR5 Registering Clock Driver to Advance Server Memory Performance (Wednesday, February 1, 2023)
• UMC and Cadence Collaborate on 3D-IC Hybrid Bonding Reference Flow (Tuesday, January 31, 2023)
• Chiplet Pioneer Eliyan Joins UCIe and JEDEC Industry Standardization Organizations, Expands Veteran Leadership Team to Accelerate Adoption of Breakthrough Die-to-Die Interconnect Solution (Monday, January 30, 2023)
• All the PCIe 5.0 SSDs Coming Out in the Next Year or So (Sunday, January 8, 2023)
• SNIA Spec Gets Data Moving in CXL Environment (Wednesday, January 4, 2023)
• PEZY Computing Selects proteanTecs to Monitor Die-to-Die Interconnects in Next-Generation Supercomputer Processors (Tuesday, December 20, 2022)
• Are You Ready for PCIe 6.0? (Wednesday, November 16, 2022)
• Alphawave IP Receives 2022 TSMC OIP Partner of the Year Award for High-Speed SerDes IP Innovations (Tuesday, November 8, 2022)
• Arteris FlexNoC Interconnect Licensed by Microchip Technology for Microcontroller Development (Tuesday, November 1, 2022)
• Synopsys Collaborates with TSMC to Unleash System Innovation with Most Comprehensive Multi-Die Design Solutions for TSMC's Advanced Technologies (Wednesday, October 26, 2022)
• GUC GLink™ Chip Leverages proteanTecs' Die-to-Die Interconnect Monitoring (Wednesday, October 26, 2022)
• Siemens Tessent Multi Die Automates 2.5D and 3D Chip DFT (Tuesday, October 25, 2022)
• GUC Unveils GLink 2.3LL, The World's Most Powerful D2D Interconnect IP Using 2.5D Technology (Tuesday, October 25, 2022)
• Intel's Road to a Universal Quantum Computer Is Via Chiplets (Monday, October 10, 2022)
• Intel plans 3nm chiplet for satellite terminal (Monday, October 10, 2022)
• CEO interview: Alphawave IP's Pialis on chiplets and custom silicon (Tuesday, September 20, 2022)
• CEO interview: Alphawave IPs Pialis on chiplets and custom silicon (Monday, September 19, 2022)
• €16m project to secure the chiplet supply chain in Europe (Monday, September 19, 2022)
• proteanTecs Joins UCIe™ (Universal Chiplet Interconnect Express™) Consortium to Advance 2.5D/3D Interconnect Monitoring (Sunday, September 18, 2022)
• Intel's new 3D Foveros packaging tech: LEGO-like chiplets for CPUs (Monday, August 22, 2022)
• Rambus Expands Portfolio of DDR5 Memory Interface Chips for Data Centers and PCs (Monday, July 18, 2022)
• Innolink - The advanced Chiplet solution complies with the Universal Chiplet Interconnect Express (UCIe) standard (Wednesday, July 6, 2022)
• GUC Demonstrate World's First HBM3 PHY, Controller, and CoWoS Platform at 7.2 Gbps (Wednesday, July 6, 2022)
• Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet applications to Achieve Compliance and High-Speed Connectivity (Monday, June 20, 2022)
• Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol (Wednesday, June 15, 2022)
• OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium (Wednesday, June 15, 2022)
• SmartDV Charts Course Toward Chiplets, Joins Universal Chiplet Interconnect Express (UCIe) (Wednesday, June 15, 2022)
• Alphawave IP Announces Availability of Two New Interconnect IP Products in TSMC Advanced Processes (Sunday, June 12, 2022)
• CEA-Leti & Intel Report Die-to-Wafer Self-Assembly Breakthrough Targeting High Alignment Accuracy and Throughput (Wednesday, June 1, 2022)
• MediaTek Launches First mmWave Chipset for Seamless 5G Smartphone Connectivity (Sunday, May 22, 2022)
• Chiplets Get a Formal Standard with UCIe 1.0 (Sunday, April 10, 2022)
• Chiplets Get a Formal Standard with UCIe 1.0 (Sunday, April 10, 2022)
• VeriSilicon Joins the Universal Chiplet Interconnect Express Industry Consortium (Sunday, April 3, 2022)
• eTopus Announces PCIe IP Gen 1-6 and 800G Support For 7/6nm With Support For SoC & Chiplet Clients (Monday, March 28, 2022)
• GUC Announces 2.5D and 3D Multi-Die APT Platform for AI, HPC, Networking ASICs (Wednesday, March 9, 2022)
• Leaders in Semiconductors, Packaging, IP Suppliers, Foundries, and Cloud Service Providers Join Forces to Standardize Chiplet Ecosystem (Wednesday, March 2, 2022)
• eTopus Announces Collaborative IP Platform for Rapid and Economical Deployment of Chiplets (Tuesday, February 1, 2022)
• CEVA Introduces Security IP for Die-to-Die Communication Between Chiplets (Tuesday, January 25, 2022)
• CXL Consortium Showcases First Public Demonstrations of Compute Express Link Technology at SC21 (Thursday, November 18, 2021)
• Analog Bits to Demonstrates Low Latency PCIe/CXL Gen 5 on Samsung 8nm at SAFE Forum 2021 (Monday, November 15, 2021)
• Heterogeneous Computing Is About Optimizing Resources (Sunday, November 7, 2021)
• Blue Cheetah Bunch-of-Wires (BoW) Chiplet Interface Solution Targets Rapid Flexibility, Scalability, and Low Overhead (Thursday, October 28, 2021)
• Rambus Advances Server Memory Performance with the Industry's First 5600 MT/s DDR5 Registering Clock Driver (Tuesday, October 12, 2021)
• Alphawave IP announces production availability of new PCIe-CXL solution on TSMC N5 process for storage and broader chiplet market (Tuesday, October 12, 2021)
• Synopsys Accelerates Multi-Die Designs with Industry's First Complete HBM3 IP and Verification Solutions (Wednesday, October 6, 2021)
• Cadence Accelerates System Innovation with Breakthrough Integrity 3D-IC Platform (Wednesday, October 6, 2021)
• Interlaken IP Core for high-speed chip-to-chip applications is now available (Wednesday, October 6, 2021)
• Rambus Delivers CXL 2.0 Controller with Industry-leading Zero-Latency IDE (Tuesday, October 5, 2021)
• Chiplet Strategy is Key to Addressing Compute Density Challenges (Tuesday, September 28, 2021)