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RISC-V News

• RISC-V IP Core: T2M to Present Production-Proven RISC-V IP Core at Mobile World Congress, 2026 (Monday, February 9, 2026)
• Fabless Startup Aheesa Tapes Out First Indian RISC-V Network SoC (Monday, February 9, 2026)
• Phison Selects Andes RISC-V Cores for its First aiDAPTIV+ AI Solution, Marking a Major Milestone in AI Architecture (Monday, February 9, 2026)
• Andes Technology Launches RISC-V Now! — A Global Conference Series Focused on Commercial, Production-Scale RISC-V (Tuesday, February 3, 2026)
• MIPS accelerates the development timeline of the RISC-V NPU S8200, integrating Synopsys ARC IP to transform into a "physical AI" computing platform. (Monday, February 2, 2026)
• TGE302 RISC-V IP Core: M0+, Comparable Performance Low-Power General-Purpose Processor (Monday, February 2, 2026)
• The OpenHW Foundation unveils the first industry-ready RISC-V ecosystem to advance European digital sovereignty (Thursday, January 29, 2026)
• MIPS Takes ‘Software-First Approach’ With New RISC-V NPUs (Thursday, January 29, 2026)
• Nuclei Announces Strategic Global Expansion to Accelerate RISC-V Adoption in 2026 (Wednesday, January 28, 2026)
• SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion (Monday, January 19, 2026)
• LTSCT and Andes Technology Sign Strategic IP Licensing Master Agreement to accelerate RISC-V Based Advanced Semiconductor Solutions (Tuesday, January 13, 2026)
• 6 Snapshots Show RISC-V Solidifying Its Stronghold in Products and Plans (Monday, January 12, 2026)
• T2M Presents TGE100 RISC-V CPU Core: Ultra-Low-Power Computing for Area-Constrained IoT and MCU Platforms (Monday, January 12, 2026)
• Quintauris and SiFive Announce Partnership to Advance RISC-V Ecosystem Development (Monday, January 12, 2026)
• Quintauris Demonstrates RISC-V Innovation in Automotive at CES (Monday, January 12, 2026)
• Meta and Qualcomm push RISC-V market share towards 25% (Thursday, January 8, 2026)
• Arm sheds billions in market capitalization after Qualcomm hints at RISC-V adoption with Ventara Micro acquisition (Monday, December 22, 2025)
• India Launches DHRUV64, First Indigenous 64-Bit Dual-Core Processor (Friday, December 19, 2025)
• VeriSilicon responds to the termination of the acquisition of Nuclei Smart Fusion: The RISC-V business layout plan remains unchanged, and the Point Semiconductor merger is proceeding concurrently. (Thursday, December 18, 2025)
• India Unveils DHRUV64: Nation’s First Indigenous 64-Bit Dual-Core Microprocessor (Thursday, December 18, 2025)
• SiFive and IAR Collaborate to Advance the Automotive Ecosystem and Drive RISC-V Innovation in Automotive Electronics (Thursday, December 18, 2025)
• ISOLDE Project Demonstrates Advancements in European Open-Source RISC-V for Automotive, Space, and IoT (Monday, December 15, 2025)
• Quintauris and SiFive Announce Partnership to Advance RISC-V Ecosystem Development (Monday, December 15, 2025)
• Qualcomm Acquires Ventana Micro Systems, Deepening RISC-V CPU Expertise (Thursday, December 11, 2025)
• India Paves Dual RISC-V Tracks with C-DAC and Startup Silicon (Thursday, December 11, 2025)
• Tenstorrent Blackhole Support & Other New RISC-V + ARM64 Hardware In Linux 6.19 (Thursday, December 11, 2025)
• Risc-v Cores and Neuromorphic Arrays Enable Scalable Digital Processors for EdgeAI Applications (Monday, December 8, 2025)
• Tenstorrent QuietBox tested: A high-performance RISC-V AI workstation trapped in a software blackhole (Thursday, November 27, 2025)
• Codasip announces strategic licensing agreement with EnSilica for its CHERI-enabled embedded CPU from the 700 family (Thursday, November 27, 2025)
• Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security (Monday, November 24, 2025)
• Breker Verification Systems and Frontgrade Gaisler Collaborate on High-Reliability RISC-V Fault-Tolerant Processor Core (Thursday, November 20, 2025)
• proteanTecs and Akeana Announce Joint Initiative to Drive Next-Generation RISC-V Processor Performance (Thursday, November 20, 2025)
• RISC-V And Its Modularity Shine Across Applications (Thursday, November 20, 2025)
• lowRISC® and Partners to Deliver Commercial-Quality, Open-Source CHERI Secure Enclave with InnovateUK Support (Thursday, November 13, 2025)
• RISC-V Summit spurs new round of automotive support (Thursday, November 6, 2025)
• The next RISC-V processor frontier: AI (Monday, November 3, 2025)
• CAST looks to simplify RISC-V IP adoption with new program (Monday, October 27, 2025)
• RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status (Monday, October 27, 2025)
• RISC-V Exceeding Expectations in AI, China Deployment (Thursday, October 23, 2025)
• Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing (Thursday, October 23, 2025)
• Arteris and Alibaba DAMO Academy Extend Partnership to Accelerate High-Performance RISC-V SoC Designs (Wednesday, October 22, 2025)
• Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing (Monday, October 20, 2025)
• Andes Showcases Expanding RISC-V Ecosystem and Next-Generation "Cuzco" High-Performance CPU at RISC-V Summit North America 2025 (Monday, October 20, 2025)
• Breker Donates Advanced Test Suite Components to RISC-V International for Use in Future Compliance Activities (Thursday, October 16, 2025)
• RISC-V set to announce 25% market penetration - open-standard ISA is ahead of schedule, securing fast-growing silicon footprint (Thursday, October 9, 2025)
• Europe Achieves a Key Milestone with the Europe's First Out-of-Order RISC-V Processor chip, with the eProcessor Project (Thursday, October 9, 2025)
• What Meta's Purchase of Rivos Says About RISC-V (Thursday, October 9, 2025)
• Tenstorrent Productizes RISC-V CPU And AI IP (Thursday, September 25, 2025)
• 22nm RISC-V AI Chip Targets Wearables and IoT (Friday, September 19, 2025)
• RISC-V: Shaping the Future of Mobility with Open Standards and Strong Partnership (Thursday, September 18, 2025)