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RISC-V News

• India Launches DHRUV64, First Indigenous 64-Bit Dual-Core Processor (Friday, December 19, 2025)
• VeriSilicon responds to the termination of the acquisition of Nuclei Smart Fusion: The RISC-V business layout plan remains unchanged, and the Point Semiconductor merger is proceeding concurrently. (Thursday, December 18, 2025)
• India Unveils DHRUV64: Nation’s First Indigenous 64-Bit Dual-Core Microprocessor (Thursday, December 18, 2025)
• SiFive and IAR Collaborate to Advance the Automotive Ecosystem and Drive RISC-V Innovation in Automotive Electronics (Thursday, December 18, 2025)
• ISOLDE Project Demonstrates Advancements in European Open-Source RISC-V for Automotive, Space, and IoT (Monday, December 15, 2025)
• Quintauris and SiFive Announce Partnership to Advance RISC-V Ecosystem Development (Monday, December 15, 2025)
• Qualcomm Acquires Ventana Micro Systems, Deepening RISC-V CPU Expertise (Thursday, December 11, 2025)
• India Paves Dual RISC-V Tracks with C-DAC and Startup Silicon (Thursday, December 11, 2025)
• Tenstorrent Blackhole Support & Other New RISC-V + ARM64 Hardware In Linux 6.19 (Thursday, December 11, 2025)
• Risc-v Cores and Neuromorphic Arrays Enable Scalable Digital Processors for EdgeAI Applications (Monday, December 8, 2025)
• Tenstorrent QuietBox tested: A high-performance RISC-V AI workstation trapped in a software blackhole (Thursday, November 27, 2025)
• Codasip announces strategic licensing agreement with EnSilica for its CHERI-enabled embedded CPU from the 700 family (Thursday, November 27, 2025)
• Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security (Monday, November 24, 2025)
• Breker Verification Systems and Frontgrade Gaisler Collaborate on High-Reliability RISC-V Fault-Tolerant Processor Core (Thursday, November 20, 2025)
• proteanTecs and Akeana Announce Joint Initiative to Drive Next-Generation RISC-V Processor Performance (Thursday, November 20, 2025)
• RISC-V And Its Modularity Shine Across Applications (Thursday, November 20, 2025)
• lowRISC® and Partners to Deliver Commercial-Quality, Open-Source CHERI Secure Enclave with InnovateUK Support (Thursday, November 13, 2025)
• RISC-V Summit spurs new round of automotive support (Thursday, November 6, 2025)
• The next RISC-V processor frontier: AI (Monday, November 3, 2025)
• CAST looks to simplify RISC-V IP adoption with new program (Monday, October 27, 2025)
• RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status (Monday, October 27, 2025)
• RISC-V Exceeding Expectations in AI, China Deployment (Thursday, October 23, 2025)
• Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing (Thursday, October 23, 2025)
• Arteris and Alibaba DAMO Academy Extend Partnership to Accelerate High-Performance RISC-V SoC Designs (Wednesday, October 22, 2025)
• Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing (Monday, October 20, 2025)
• Andes Showcases Expanding RISC-V Ecosystem and Next-Generation "Cuzco" High-Performance CPU at RISC-V Summit North America 2025 (Monday, October 20, 2025)
• Breker Donates Advanced Test Suite Components to RISC-V International for Use in Future Compliance Activities (Thursday, October 16, 2025)
• RISC-V set to announce 25% market penetration - open-standard ISA is ahead of schedule, securing fast-growing silicon footprint (Thursday, October 9, 2025)
• Europe Achieves a Key Milestone with the Europe's First Out-of-Order RISC-V Processor chip, with the eProcessor Project (Thursday, October 9, 2025)
• What Meta's Purchase of Rivos Says About RISC-V (Thursday, October 9, 2025)
• Tenstorrent Productizes RISC-V CPU And AI IP (Thursday, September 25, 2025)
• 22nm RISC-V AI Chip Targets Wearables and IoT (Friday, September 19, 2025)
• RISC-V: Shaping the Future of Mobility with Open Standards and Strong Partnership (Thursday, September 18, 2025)
• Infineon Reportedly Set to Build RISC-V Auto MCUs at TSMC Dresden Fab, Mass Production in 2028 (Monday, September 15, 2025)
• RISC-V IP expands AI capabilities at the edge (Monday, September 15, 2025)
• SiFive details second generation RISC-V cores for AI accelerators (Tuesday, September 9, 2025)
• Linus Torvalds Rejects RISC-V Changes For Linux 6.17: "Garbage" (Saturday, August 9, 2025)
• NVIDIA on RVA23: "We Wouldn't Have Considered Porting CUDA to RISC-V Without It" (Thursday, August 7, 2025)
• 7 Critical Components of the Car of Tomorrow (Tuesday, August 5, 2025)
• China Unyielding Ascent in RISC-V (Tuesday, August 5, 2025)
• MIPS and Cyient Collaborate on RISC-V Power Solutions (Friday, July 25, 2025)
• China Emerging as Significant Force in RISC-V Development and Adoption (Friday, July 25, 2025)
• NVIDIA's CUDA Now Supports RISC-V Processors in AI Systems, Marking a Major Development & Posing a Threat to the x86 and ARM Duopoly (Saturday, July 19, 2025)
• RISC-V Solidifies Presence in China as Global Momentum Builds (Friday, July 11, 2025)
• Andes Technology's AutoOpTune™ Applies Genetic Algorithms to Accelerate RISC-V Software Optimization (Thursday, July 10, 2025)
• 160-core RISC V Board Is The M.2 CoProcessor You Didn't Know You Needed (Monday, July 7, 2025)
• Are open-source RISC-V CPUs a threat to ARM Holdings' business? (Friday, July 4, 2025)
• RISC-V and AI: Innatera's PULSAR Shakes Up the Edge (Tuesday, June 24, 2025)
• IAR Platform Accelerates Embedded Development with Updated Toolchains for Arm and RISC-V (Tuesday, June 10, 2025)
• Andes Technology Announces AndeSight™ IDE v5.4 to Streamline AI and Embedded Software Development on RISC-V (Tuesday, June 10, 2025)