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RISC-V News

• MIPS Announces Availability of its first RISC-V IP core - the eVocore P8700 Multiprocessor (Sunday, December 11, 2022)
• Codasip launches SecuRISC5 initiative (Sunday, December 11, 2022)
• Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification (Sunday, December 11, 2022)
• QuarkLink scalable IoT Security Platform Now Available on 30-Day Free Trial (Sunday, December 11, 2022)
• Microchip Showcases RISC-V-Based FPGA and Space-Compute Solutions at RISC-V Summit (Sunday, December 11, 2022)
• Imperas and Imagination collaborate on providing virtual platform models for the Catapult RISC-V CPU family (Wednesday, December 7, 2022)
• Andes Announces RISC-V Multicore 1024-bit Vector Processor: AX45MPV (Wednesday, December 7, 2022)
• Intel Pathfinder for RISC-V unifies platform, adds features (Tuesday, December 6, 2022)
• MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors (Tuesday, December 6, 2022)
• Codasip launches Codasip Labs to accelerate advanced technologies (Tuesday, December 6, 2022)
• Intel Pathfinder for RISC-V: New Capabilities and A Growing Ecosystem (Monday, December 5, 2022)
• Imperas and Andes collaborate to support RISC-V innovations (Sunday, December 4, 2022)
• Codasip and Intel bring RISC-V development to higher-education (Thursday, December 1, 2022)
• USB IP Cores for the Intel Pathfinder for RISC-V Platform (Thursday, December 1, 2022)
• CEVA Joins Intel Pathfinder for RISC-V Program (Wednesday, November 30, 2022)
• RISC-V Summit 2022: Codasip to showcase processor customization, and safety and security solutions (Monday, November 28, 2022)
• CAES Design Win of RISC-V/NOEL-V IP for Idaho Scientific Secure Processor for US Critical Infrastructure (Monday, November 28, 2022)
• Cortus announces the launch of LOTUS family with two new RISC-V microcontrollers (MCUs) (Sunday, November 27, 2022)
• RISC-V Is Far from Being an Alternative to x86 and Arm in HPC (Thursday, November 17, 2022)
• Why RISC-V Architecture Is the Future of Embedded Design (Wednesday, November 16, 2022)
• Small code, high performance: Latest IAR Embedded Workbench for RISC-V leverages CoDense™ from Andes (Wednesday, November 16, 2022)
• NASA Uses RISC-V Vector Spec to Soup Up Space Computers (Monday, November 14, 2022)
• Codasip to boost RISC-V security through Cerberus acquisition (Wednesday, November 9, 2022)
• SiFive Awarded TSMC Open Innovation Platform Partner of the Year (Wednesday, November 2, 2022)
• With its New RISC-V Processors, SiFive Bets on Compute Density (Tuesday, November 1, 2022)
• Andes Technology Unveils The AndesCore® AX60 Series, An Out-Of-Order Superscalar Multicore RISC-V Processor Family (Tuesday, November 1, 2022)
• Codasip delivers custom RISC-V processing to SiliconArts ray-tracing GPUs (Tuesday, November 1, 2022)
• SiFive's New High-Performance Processors Offer a Significant Upgrade for Wearable and Consumer Products (Monday, October 31, 2022)
• Blueshift to demo high speed memory in RISC-V ASIC for computer vision (Tuesday, October 25, 2022)
• IAR Systems' Functional Safety Certified Development Tools for RISC-V support latest SiFive Automotive Solutions (Tuesday, October 25, 2022)
• SiFive and Synopsys Collaborate to Accelerate SoC Design (Monday, October 24, 2022)
• SEGGER introduces streaming trace probe for SiFive RISC-V cores (Monday, October 24, 2022)
• RISC-V Celebrates Upstreaming of Android Open Source Project RISC-V Port (Sunday, October 23, 2022)
• IAR Systems' Functional Safety Certified Development Tools for RISC-V support the latest SiFive Automotive Solutions (Monday, October 17, 2022)
• 'First' RISC-V CPU certified compliant with ISO 26262 (Sunday, October 16, 2022)
• First RISC-V laptop uses Alibaba TH1520 SoC (Sunday, October 16, 2022)
• Andes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance (Sunday, October 16, 2022)
• French secure element processor uses RISC-V (Tuesday, October 11, 2022)
• Andes Technology Announces Return of the Annual RISC-V CON on October 18th in the San Jose Airport DoubleTree Hotel (Monday, October 10, 2022)
• Tiempo Secure becomes a Strategic Member of RISC-V International (Monday, October 10, 2022)
• Intel Horse Creek platform showcased with SiFive P550 RISC-V CPU, 8GB DDR5, PCIe Gen5 (Sunday, October 9, 2022)
• It's Time to Consider RISC-V (Thursday, October 6, 2022)
• SEGGER licenses C++ runtime library to SiFive for code size and performance efficiency (Wednesday, September 28, 2022)
• SiFive and ProvenRun Collaborate to deliver Best-in-Class Security for RISC-V Microprocessors (Monday, September 26, 2022)
• ST, CAES team on octacore RISC-V space chip with selectable cores (Thursday, September 22, 2022)
• Arm Is The New RISC/Unix, RISC-V Is The New Arm (Wednesday, September 21, 2022)
• Codasip joins OpenHW Group to contribute to RISC-V verification (Tuesday, September 20, 2022)
• VisionFive 2 will be made compatible with all mainstream Linux Operating Systems (Sunday, September 18, 2022)
• SiFive Rolls Out Powerful New RISC-V Portfolio to Address Unmet Performance and Feature Needs of Rapidly Evolving Next-Gen Digital Automobiles (Monday, September 12, 2022)
• Cortus Announces the Launch of its New Secure Low Power RISC-V Microcontrollers (Sunday, September 11, 2022)