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RISC-V News

• The European Space Agency (ESA) has awarded a contract to CAES, in the frame of the ARTES Competitiveness & Growth programme, to develop System-on-Chip for space applications (Tuesday, December 21, 2021)
• StarFive Released Open-Sourced Dubhe Linux SDK in RVspace Community (Wednesday, December 15, 2021)
• New RISC-V verification product changes the fabric of processor DV (Monday, December 13, 2021)
• China's road to homegrown chip glory looks to be going for a RISC-V future (Wednesday, December 8, 2021)
• RISC-V Celebrates Incredible Year of Growth and Progress, Ratifying Multiple Technical Specifications, Launching New Education Programs, and Accelerating Broad Industry Adoption (Wednesday, December 8, 2021)
• StarFive VisionFive Single Board Computer Officially for Sale, Accelerating RISC-V Ecosystem Development (Wednesday, December 8, 2021)
• SEGGER adds 64-bit RISC-V support to Embedded Studio (Wednesday, December 8, 2021)
• StarFive Starts Delivery of High Performance RISC-V CPU Core IP "Dubhe" (Tuesday, December 7, 2021)
• SoC design for AI-based applications using RISC-V Vector processors (Monday, December 6, 2021)
• SiFive Expands and Improves Industry-Leading RISC-V Processor Portfolio (Monday, December 6, 2021)
• Fraunhofer extends RISC-V embedded processor for edge AI (Sunday, December 5, 2021)
• Imagination launches RISC-V CPU family (Sunday, December 5, 2021)
• Imperas releases new RISC-V verification product that changes the fabric of processor DV (Sunday, December 5, 2021)
• Ashling RiscFree now supports Andes Technology RISC-V CPUs (Sunday, December 5, 2021)
• Fraunhofer IPMS and CAST Announce a RISC-V Embedded Processor for Edge AI (Sunday, December 5, 2021)
• HPMicro Semiconductor Announces the Release of the HPM6000 Series of Microcontrollers with AndesCore Dual D45 Cores (Wednesday, December 1, 2021)
• SiFive Raises RISC-V performance bar with New Best-in-Class SiFive Performance P650 Processor (Wednesday, December 1, 2021)
• RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs (Wednesday, December 1, 2021)
• Andes RISC-V Superscalar Multicore A(X)45MP and Vector Processor NX27V Upgrade Their Spec. and Performance (Wednesday, December 1, 2021)
• HPMicro Semiconductor Announces the Release of the HPM6000 series of Microcontrollers with AndesCore™ dual D45 cores (Wednesday, December 1, 2021)
• IAR Systems and Codasip collaborate to enable low-power RISC-V based applications (Monday, November 29, 2021)
• MIPS selects Imperas Reference Models for RISC-V Processor Verification (Monday, November 29, 2021)
• First RISC-V smartphones could launch in 2022 (Thursday, November 25, 2021)
• AMIQ EDA Joins OpenHW Group and Contributes Linting Capabilities for CORE-V Open-Source RISC-V Cores and Testbenches (Wednesday, November 24, 2021)
• Microchip Adds Second Development Tool Offering for Designers Using Its Low-Power PolarFire RISC-V SoC FPGA for Embedded Vision Applications at the Edge (Monday, November 22, 2021)
• Codasip Adopts Imperas for RISC-V Processor Verification (Sunday, November 21, 2021)
• Reference models for newly ratified RISC-V Specifications (Wednesday, November 17, 2021)
• Imperas Models - reference for the newly ratified RISC-V Specifications (Wednesday, November 17, 2021)
• RISC-V Low-Power Embedded Processor IP Core Now Available from CAST (Tuesday, November 16, 2021)
• Kneron Edge AI SoC Powered by Andes RISC-V Processor Core D25F (Monday, November 8, 2021)
• NSITEXE DR1000C, a RISC-V based parallel processor IP with vector extension (DFP: Data Flow Processor) has been licensed for Renesas' new RH850/U2B Automotive MCUs (Monday, November 8, 2021)
• Codasip expands ecosystem with XtremeEDA (Wednesday, November 3, 2021)
• Codasip appoints Brett Cline to drive company growth worldwide (Monday, November 1, 2021)
• Truechip Introduces Silicon IP For Network on Chip (NoC) Focussed For Tilelink RISC-V Chips (Thursday, October 28, 2021)
• Codasip Founder Karel Masarik elected to RISC-V Technical Steering Committee (Wednesday, October 27, 2021)
• SiFive has briefly pulled back the curtains on its most powerful Risc-V processor yet. (Wednesday, October 27, 2021)
• New Allwinner RISC-V Chip Uncovered on Tiny Board (Monday, October 25, 2021)
• Codasip boosts custom RISC-V performance in latest tool (Monday, October 25, 2021)
• Codasip boosts Studio processor design tools with AXI automation (Monday, October 25, 2021)
• Functional safety tools certified on RISC-V (Sunday, October 24, 2021)
• IAR Systems extends functional safety offering for RISC-V with leading build tools for Linux (Sunday, October 24, 2021)
• De-RISC, the H2020 project which will create the first RISC-V fully European platform for aerospace, celebrates its second anniversary (Tuesday, October 19, 2021)
• RISC-V player announces expansion of US operation (Tuesday, October 12, 2021)
• Intel backs RISC-V for Nios FPGA processor (Wednesday, October 6, 2021)
• Green Hills Software Expands INTEGRITY Support to Include RISC-V Architecture (Wednesday, October 6, 2021)
• Codasip Announces UK Hiring for RISC-V Development (Monday, October 4, 2021)
• 6,000 RISC-V Cores on a Xilinx FPGA Break the CoreScore World Record (Monday, September 27, 2021)
• Bluespec, Inc. Releases Ultra-Low Footprint RISC-V Processor Family for Xilinx FPGAs, Offers Free Quick-Start Evaluation. (Monday, September 27, 2021)
• EPI EPAC1.0 RISC-V Test Chip Samples Delivered (Tuesday, September 21, 2021)
• RISC-V to Shake Up $8.6B Semiconductor IP Market (Monday, September 20, 2021)