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RISC-V News

• Menta and Andes Announce Partnership Enabling Hardware Reconfiguring for ISA Extension (Monday, December 7, 2020)
• OneSpin Contributes to the OpenHW Ecosystem to Achieve Processor Integrity for the CORE-V CVE4 Open-Source RISC-V Cores (Monday, December 7, 2020)
• Andes RISC-V Vector Processor NX27V Is Upgraded to RVV 1.0 (Wednesday, December 2, 2020)
• 64-bit RISC-V Core Claims to Outperform Apple M1 SoC (Tuesday, December 1, 2020)
• IAR Systems delivers extended optimization and trace capabilities for RISC-V development (Wednesday, November 25, 2020)
• Bouffalo Lab Standardizes on SiFive RISC-V Embedded CPU Core IP for New IoT Products (Tuesday, November 17, 2020)
• First steps to European multicore RISC-V chip for space (Sunday, November 15, 2020)
• Alibaba's Ultra High-Performance Superscalar Processor - XuanTie910 (Sunday, November 15, 2020)
• De-RISC first anniversary, a H2020 project which will create the first RISC-V, fully European platform for space (Wednesday, November 11, 2020)
• Open-Source RISC-V ISA Offers More (Thursday, November 5, 2020)
• Telink TLSR9 Wireless Audio & IoT RISC-V SoC integrates RISC-V DSP/SIMD P-extension (Tuesday, November 3, 2020)
• World's fastest 64bit RISC-V core claims 5GHz speed (Tuesday, October 27, 2020)
• Truechip Adds New Customer Shipments of Verification IPs For RISC-V Family Including TileLink (Tuesday, October 27, 2020)
• Nvidia-Arm Deal a Boon for RISC-V? (Sunday, October 25, 2020)
• Micro Magic, Inc. Unleashes World's Fastest RISC-V Core (Sunday, October 25, 2020)
• IAR Systems brings functional safety tools to RISC-V with certification for IEC 61508 and ISO 26262 (Tuesday, October 20, 2020)
• riscvOVPsim gets Risc-V vector instructions (Sunday, October 18, 2020)
• Think Silicon to introduce a new Inference Micro GPU Architecture based on RISC-V at Linley Fall Virtual Processor Conference (Wednesday, October 7, 2020)
• Renesas Selects Andes RISC-V 32-Bit CPU Cores for its First RISC-V Implementation of ASSPs (Wednesday, September 30, 2020)
• Is RISC-V Processor Hardware or Software? (Tuesday, September 29, 2020)
• Creating Domain Specific Processors Using Custom RISC-V ISA Instructions (Sunday, September 27, 2020)
• The Incredible Opportunity For SiFive (Wednesday, September 16, 2020)
• The Industry's First SoC FPGA Development Kit Based on the RISC-V Instruction Set Architecture is Now Available (Tuesday, September 15, 2020)
• New PicoRio SBC To Feature RISC-V Open-Source Processor (Saturday, September 5, 2020)
• SiFive and Barcelona Supercomputing Center Advance Industry Adoption of RISC-V Vector Extension (Wednesday, September 2, 2020)
• Imagination announces the first RISC-V computer architecture course (Tuesday, September 1, 2020)
• Alibaba's new 16-core CPU will challenge Intel Xeon in datacenters (Thursday, August 27, 2020)
• Bluespec, Inc. Releases RISC-V Explorer: A Fast, Free, Accurate Way to Evaluate RISC-V (Wednesday, August 26, 2020)
• Alibaba XT910 RISC-V Core Faster Than Kirin 970 SoC; Threat To ARM? (Tuesday, August 18, 2020)
• RIOS Laboratory and Imagination announce partnership to grow the RISC-V ecosystem (Tuesday, August 18, 2020)
• SiFive founds business unit to mix Risc-V and Arm cores on silicon (Sunday, August 16, 2020)
• One on One with RISC-V CTO Mark Himelstein (Sunday, August 9, 2020)
• Codasip and Metrics Design Automation Announce the Integration of the Metrics Cloud Simulation Platform in Codasip's RISC-V SweRV CORE Support Package Pro (Tuesday, August 4, 2020)
• x86, ARM, and RISC-V software running on Tachyum Prodigy (Tuesday, August 4, 2020)
• Picocom Embeds 32 Andes N25F RISC-V Cores into Its 5G NR Small Cell Baseband SoC (Monday, August 3, 2020)
• Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRO (Wednesday, July 22, 2020)
• SiFive Elevates Custom SoC Design With Enhanced Processor IP Portfolio (Wednesday, July 22, 2020)
• OpenHW Ecosystem Implements Imperas RISC-V reference models for Coverage Driven Verification of Open Source CORE-V processor IP cores (Tuesday, July 21, 2020)
• Codasip Releases the First Linux-Capable RISC-V Core Bk7 Optimized for Domain-Specific Applications (Monday, July 20, 2020)
• Axiomise Announces the Release of the Next-Generation RISC-V App (Wednesday, July 15, 2020)
• Axiomise Announces the Release of the Next-Generation RISC-V® App (Monday, July 13, 2020)
• SiFive looks to foster worldwide network of RISC-V startups (Tuesday, July 7, 2020)
• IAR Systems enables secure code with updated MISRA C compliance in leading development tools (Sunday, June 14, 2020)
• A guide to accelerating applications with just-right RISC-V custom instructions (Thursday, June 11, 2020)
• RISC-V crypto core is qualified to ASIL-D for automotive designs (Tuesday, June 9, 2020)
• IAR Systems and GigaDevice collaborate to bring powerful RISC-V solutions to the market (Monday, June 8, 2020)
• The Increasingly Ordinary Task Of Verifying RISC-V (Tuesday, June 2, 2020)
• Efinix Announces Availability of Three RISC-V SoCs (Tuesday, June 2, 2020)
• Collaboration focuses on development tools for RISC-V-based MCUs (Monday, June 1, 2020)
• Codasip Extends SweRV Support Package to Include Western Digital SweRV EH2 & EL2 RISC-V Cores (Monday, June 1, 2020)