Search News

RISC-V News

• Creating Domain Specific Processors Using Custom RISC-V ISA Instructions (Sunday, September 27, 2020)
• The Incredible Opportunity For SiFive (Wednesday, September 16, 2020)
• The Industry's First SoC FPGA Development Kit Based on the RISC-V Instruction Set Architecture is Now Available (Tuesday, September 15, 2020)
• New PicoRio SBC To Feature RISC-V Open-Source Processor (Saturday, September 5, 2020)
• SiFive and Barcelona Supercomputing Center Advance Industry Adoption of RISC-V Vector Extension (Wednesday, September 2, 2020)
• Imagination announces the first RISC-V computer architecture course (Tuesday, September 1, 2020)
• Alibaba's new 16-core CPU will challenge Intel Xeon in datacenters (Thursday, August 27, 2020)
• Bluespec, Inc. Releases RISC-V Explorer: A Fast, Free, Accurate Way to Evaluate RISC-V (Wednesday, August 26, 2020)
• Alibaba XT910 RISC-V Core Faster Than Kirin 970 SoC; Threat To ARM? (Tuesday, August 18, 2020)
• RIOS Laboratory and Imagination announce partnership to grow the RISC-V ecosystem (Tuesday, August 18, 2020)
• SiFive founds business unit to mix Risc-V and Arm cores on silicon (Sunday, August 16, 2020)
• One on One with RISC-V CTO Mark Himelstein (Sunday, August 9, 2020)
• Codasip and Metrics Design Automation Announce the Integration of the Metrics Cloud Simulation Platform in Codasip's RISC-V SweRV CORE Support Package Pro (Tuesday, August 4, 2020)
• x86, ARM, and RISC-V software running on Tachyum Prodigy (Tuesday, August 4, 2020)
• Picocom Embeds 32 Andes N25F RISC-V Cores into Its 5G NR Small Cell Baseband SoC (Monday, August 3, 2020)
• Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRO (Wednesday, July 22, 2020)
• SiFive Elevates Custom SoC Design With Enhanced Processor IP Portfolio (Wednesday, July 22, 2020)
• OpenHW Ecosystem Implements Imperas RISC-V reference models for Coverage Driven Verification of Open Source CORE-V processor IP cores (Tuesday, July 21, 2020)
• Codasip Releases the First Linux-Capable RISC-V Core Bk7 Optimized for Domain-Specific Applications (Monday, July 20, 2020)
• Axiomise Announces the Release of the Next-Generation RISC-V App (Wednesday, July 15, 2020)
• Axiomise Announces the Release of the Next-Generation RISC-V® App (Monday, July 13, 2020)
• SiFive looks to foster worldwide network of RISC-V startups (Tuesday, July 7, 2020)
• IAR Systems enables secure code with updated MISRA C compliance in leading development tools (Sunday, June 14, 2020)
• A guide to accelerating applications with just-right RISC-V custom instructions (Thursday, June 11, 2020)
• RISC-V crypto core is qualified to ASIL-D for automotive designs (Tuesday, June 9, 2020)
• IAR Systems and GigaDevice collaborate to bring powerful RISC-V solutions to the market (Monday, June 8, 2020)
• The Increasingly Ordinary Task Of Verifying RISC-V (Tuesday, June 2, 2020)
• Efinix Announces Availability of Three RISC-V SoCs (Tuesday, June 2, 2020)
• Collaboration focuses on development tools for RISC-V-based MCUs (Monday, June 1, 2020)
• Codasip Extends SweRV Support Package to Include Western Digital SweRV EH2 & EL2 RISC-V Cores (Monday, June 1, 2020)
• Don't Let Baggage Hinder Innovation: RISC-V Lets Us Start with a Clean Slate (Sunday, May 31, 2020)
• Domain Specific Accelerators Will Drive Vector Processing on RISC-V (Tuesday, May 26, 2020)
• Mirabilis Design creates the first RISC-V system-level architecture exploration solution (Tuesday, May 19, 2020)
• Imperas Leading RISC-V CPU Reference Model for Hardware Design Verification Selected by Mellanox (Monday, April 20, 2020)
• Andes Technology Announces over 5 Billion Cumulative Shipments of SoCs Embedded with Its CPU IP since Company Inception (Monday, March 30, 2020)
• RISC-V is Here to Stay (Wednesday, March 18, 2020)
• Open source of trouble: China's efforts to decouple from foreign IT technologies (Tuesday, March 17, 2020)
• Trace and debug claim for RISC-V IP challenged by UltraSoC (Tuesday, March 17, 2020)
• Codasip Awarded European Union Horizon 2020 Funding for Developing New RISC-V Processors (Tuesday, March 17, 2020)
• RISC-V Foundation Announces Ratification of the Processor Trace Specification (Tuesday, March 10, 2020)
• Andes to Presents Andes Custom Extensions to the RISC-V V5 CPU Core for Creating Highly Competitive True Wireless Stereo SoC Designs (Tuesday, March 10, 2020)
• Espressif's 240MHz ESP32-S2 SoCs, Modules, and Boards Enter Mass Production with RISC-V Coprocessor (Sunday, March 1, 2020)
• RISC-V reference models support processor verification (Monday, February 24, 2020)
• RISC-V gaining ground (Monday, February 24, 2020)
• OpenHW Group Celebrates Rapid Growth to 40+ Members and New Open-Source Processor Implementations Less Than a Year After Launch (Monday, February 24, 2020)
• Bluespec's RISC-V Factory Proves Its Dependable Productization, Helping Calligo Technologies Harness RISC-V for Posit-enabled Computing (Wednesday, February 19, 2020)
• Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores (Tuesday, February 18, 2020)
• RVSoC Offers a Lightweight Linux-Capable RISC-V Core in Just 5,000 Lines of Verilog (Sunday, February 16, 2020)
• RISC-V Foundation Showcases Unprecedented Momentum and Growth at Embedded World 2020 (Thursday, February 6, 2020)
• Embedded controller Floating-Point Library supports RISC-V (Wednesday, February 5, 2020)