Search News

RISC-V News

• Andes Technology Takes the Lead in Launching RISC-V Total Solutions and Driving Industry-Academia Collaboration with over 120 Projects (Wednesday, January 8, 2020)
• ONiO.zero offers a RISC-V Microcontroller that runs without battery (Tuesday, January 7, 2020)
• Open Source Hardware Risks (Tuesday, January 7, 2020)
• Bluespec, Inc. to Open Source Its Proven BSV High-level HDL Tools (Monday, January 6, 2020)
• RISC-V Lagarto is First Open Source Chip Developed in Spain (Monday, December 30, 2019)
• Bluespec Unveils Groundbreaking "RISC-V Factory" - Empowering Open Source Hardware Developers to Build Faster and More Efficiently (Sunday, December 22, 2019)
• How RISC-V is creating a globally neutral, open source processor architecture (Thursday, December 19, 2019)
• Microchip unveils details and opens early access program for RISC-V enabled low-power PolarFire SoC family (Wednesday, December 18, 2019)
• Microchip PolarFire Takes a RISC (-V) (Tuesday, December 17, 2019)
• Wind River Announces RISC-V Support for VxWorks RTOS (Tuesday, December 17, 2019)
• Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors (Wednesday, December 11, 2019)
• RISC-V grows globally as an alternative to Arm and its license fees (Tuesday, December 10, 2019)
• Cobham Releases RISC-V Processor IP Core (Tuesday, December 10, 2019)
• RISC-V Xmas gifts: SiFive emits vector-enabled cores, Western Digital teases new SweRVs, VxWorks hugs ISA, Samsung rolls it into 5G... (Monday, December 9, 2019)
• Microchip Unveils Family Details and Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC FPGA Family (Monday, December 9, 2019)
• Andes' Core has RISC-V Vector Instruction Extension (Sunday, December 8, 2019)
• Andes 45-Series Expands RISC-V High-end Processors 8-Stage Superscalar Processor Balances High Performance, Power Efficiency, and Real-time Determinism with Rich RISC-V Ecosystem (Wednesday, December 4, 2019)
• SiFive To Present New Technologies At RISC-V Summit 2019 (Wednesday, December 4, 2019)
• Andes Presents Ground-Breaking 27-Series Processor at RISC-V Summit 2019 (Tuesday, December 3, 2019)
• SiFive Learn Inventor Development System Now AWS Qualified (Monday, December 2, 2019)
• Semico Forecasts Strong Growth for RISC-V (Wednesday, November 27, 2019)
• SiFive Welcomes Stuart Ching As Chief Revenue Officer (Tuesday, November 26, 2019)
• Trade dispute drives RISC-V-Foundation to Switzerland (Tuesday, November 26, 2019)
• Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V (Monday, November 25, 2019)
• SparkFun Picks SiFive's FE310 to Power RISC-V-Based RED-V Thing Plus, RED-V RedBoard Dev Boards (Friday, November 22, 2019)
• RISC-V Myths and More (Monday, November 18, 2019)
• RISC-V Not So Risky (Monday, November 18, 2019)
• RISC-V Markets, Security And Growth Prospects (Sunday, November 17, 2019)
• Secure-IC and Andes Technology jointly provide cybersecurity enhanced RISC-V cores (Tuesday, November 12, 2019)
• Aerendir Mobile Inc. and SiFive Inc. Collaborate to Accelerate the Adoption of AI-Enabled Processors (Monday, November 11, 2019)
• SiFive Announces New U8-Series Core IP For High-Performance Compute (Sunday, October 27, 2019)
• RISC-V Challenges And Opportunities (Wednesday, October 23, 2019)
• SiFive Announces New SiFive Shield For Modern SoC Design (Wednesday, October 23, 2019)
• GCC support for the draft Bit Manipulation Extension for RISC-V (Monday, October 21, 2019)
• Samsung To Fabricate RISC-V Chip With 14LPP In Partnership With SemiFive (Sunday, October 13, 2019)
• Announcing the Winners of the RISC-V Soft CPU Contest (Monday, September 30, 2019)
• Andes Technology and Tiempo Secure Announce Strategic Partnership to Enhance RISC-V Platform Security up to CC EAL5+ Certification (Monday, September 30, 2019)
• Andes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform Ecosystem Forum (Monday, September 23, 2019)
• Intensivate Engages SiFive's RISC-V Expertise to Develop Leading Accelerator (Wednesday, September 18, 2019)
• SEGGER Makes Its Entire Ecosystem of Tools Available for AndesCores (Wednesday, September 18, 2019)
• IAR Systems updates RISC-V development tools (Tuesday, September 10, 2019)
• The Journey of RISC-V Implementation (Monday, September 9, 2019)
• Veriest collaborates with MINRES on RISC-V development (Wednesday, September 4, 2019)
• Nvidia Turns to RISC-V for RC18 Research Chip IO Core (Tuesday, September 3, 2019)
• RISC-V for everybody (Tuesday, September 3, 2019)
• Seeed Releases Sipeed's Longan Nano RISC-V Development Board (Tuesday, September 3, 2019)
• Full support for first flash-based RISC-V microcontroller (Thursday, August 29, 2019)
• Researchers build RISC-V chip from carbon nanotubes (Wednesday, August 28, 2019)
• AndesCore N22 RISC-V Core Supports RV32IMAC or RV32EMAC Instruction Sets (Tuesday, August 27, 2019)
• RISC-V Is Experiencing a Period of Optimism and Growth with Global Revenue Expected to Reach $1.1 Billion by 2025, According to Tractica (Monday, August 26, 2019)