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RISC-V News

• Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores (Tuesday, February 18, 2020)
• RVSoC Offers a Lightweight Linux-Capable RISC-V Core in Just 5,000 Lines of Verilog (Sunday, February 16, 2020)
• RISC-V Foundation Showcases Unprecedented Momentum and Growth at Embedded World 2020 (Thursday, February 6, 2020)
• Embedded controller Floating-Point Library supports RISC-V (Wednesday, February 5, 2020)
• The First RISC-V Hackathon in Israel (Monday, February 3, 2020)
• High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V (Wednesday, January 29, 2020)
• SoM is built around multi-core RISC-V SoC FPGA (Tuesday, January 28, 2020)
• Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec's Riviera-PRO for HDL Simulation (Monday, January 27, 2020)
• ESP Open Source Research Platform Enables the Design of RISC-V & Sparc SoC's with Accelerators (Saturday, January 25, 2020)
• Ada and RISC-V Secure Nvidia's Future (Wednesday, January 22, 2020)
• New RISC-V Solution: SAFERTOS for IAR Embedded Workbench for RISC-V (Monday, January 20, 2020)
• Imagination Technologies charts its future with new Apple deal and post-MIPS strategy (Friday, January 17, 2020)
• How to Get Started with RISC-V-Based Microcontrollers (Wednesday, January 8, 2020)
• Andes Technology Takes the Lead in Launching RISC-V Total Solutions and Driving Industry-Academia Collaboration with over 120 Projects (Wednesday, January 8, 2020)
• ONiO.zero offers a RISC-V Microcontroller that runs without battery (Tuesday, January 7, 2020)
• Open Source Hardware Risks (Tuesday, January 7, 2020)
• Bluespec, Inc. to Open Source Its Proven BSV High-level HDL Tools (Monday, January 6, 2020)
• RISC-V Lagarto is First Open Source Chip Developed in Spain (Monday, December 30, 2019)
• Bluespec Unveils Groundbreaking "RISC-V Factory" - Empowering Open Source Hardware Developers to Build Faster and More Efficiently (Sunday, December 22, 2019)
• How RISC-V is creating a globally neutral, open source processor architecture (Thursday, December 19, 2019)
• Microchip unveils details and opens early access program for RISC-V enabled low-power PolarFire SoC family (Wednesday, December 18, 2019)
• Microchip PolarFire Takes a RISC (-V) (Tuesday, December 17, 2019)
• Wind River Announces RISC-V Support for VxWorks RTOS (Tuesday, December 17, 2019)
• Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors (Wednesday, December 11, 2019)
• RISC-V grows globally as an alternative to Arm and its license fees (Tuesday, December 10, 2019)
• Cobham Releases RISC-V Processor IP Core (Tuesday, December 10, 2019)
• RISC-V Xmas gifts: SiFive emits vector-enabled cores, Western Digital teases new SweRVs, VxWorks hugs ISA, Samsung rolls it into 5G... (Monday, December 9, 2019)
• Microchip Unveils Family Details and Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC FPGA Family (Monday, December 9, 2019)
• Andes' Core has RISC-V Vector Instruction Extension (Sunday, December 8, 2019)
• Andes 45-Series Expands RISC-V High-end Processors 8-Stage Superscalar Processor Balances High Performance, Power Efficiency, and Real-time Determinism with Rich RISC-V Ecosystem (Wednesday, December 4, 2019)
• SiFive To Present New Technologies At RISC-V Summit 2019 (Wednesday, December 4, 2019)
• Andes Presents Ground-Breaking 27-Series Processor at RISC-V Summit 2019 (Tuesday, December 3, 2019)
• SiFive Learn Inventor Development System Now AWS Qualified (Monday, December 2, 2019)
• Semico Forecasts Strong Growth for RISC-V (Wednesday, November 27, 2019)
• SiFive Welcomes Stuart Ching As Chief Revenue Officer (Tuesday, November 26, 2019)
• Trade dispute drives RISC-V-Foundation to Switzerland (Tuesday, November 26, 2019)
• Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V (Monday, November 25, 2019)
• SparkFun Picks SiFive's FE310 to Power RISC-V-Based RED-V Thing Plus, RED-V RedBoard Dev Boards (Friday, November 22, 2019)
• RISC-V Myths and More (Monday, November 18, 2019)
• RISC-V Not So Risky (Monday, November 18, 2019)
• RISC-V Markets, Security And Growth Prospects (Sunday, November 17, 2019)
• Secure-IC and Andes Technology jointly provide cybersecurity enhanced RISC-V cores (Tuesday, November 12, 2019)
• Aerendir Mobile Inc. and SiFive Inc. Collaborate to Accelerate the Adoption of AI-Enabled Processors (Monday, November 11, 2019)
• SiFive Announces New U8-Series Core IP For High-Performance Compute (Sunday, October 27, 2019)
• RISC-V Challenges And Opportunities (Wednesday, October 23, 2019)
• SiFive Announces New SiFive Shield For Modern SoC Design (Wednesday, October 23, 2019)
• GCC support for the draft Bit Manipulation Extension for RISC-V (Monday, October 21, 2019)
• Samsung To Fabricate RISC-V Chip With 14LPP In Partnership With SemiFive (Sunday, October 13, 2019)
• Announcing the Winners of the RISC-V Soft CPU Contest (Monday, September 30, 2019)
• Andes Technology and Tiempo Secure Announce Strategic Partnership to Enhance RISC-V Platform Security up to CC EAL5+ Certification (Monday, September 30, 2019)